MB90F654A FUJITSU [Fujitsu Component Limited.], MB90F654A Datasheet - Page 37

• Manufacturer Part Number: MB90F654A
• Description: 16-bit Proprietary Microcontroller
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

2. UART
• Full duplex, double buffered
• Supports asynchronous (start-stop synchronization) and CLK synchronous data transfer
• Supports multi-processor mode
• Built-in dedicated baud rate generator
• Supports flexible baud rate setting using an external clock
• Error detect function (parity, framing, and overrun)
• NRZ type transmission signal
• Intelligent I/O service support
(1) Register Configuration
The UART is a serial I/O port that can be used for CLK asynchronous (start-stop synchronization) or CLK
synchronous communications. The UART has the following features.
Serial status register 0 (SSR0)
Clock division control register (CDCR)
Serial mode register 0 (SMR0)
Serial control register 0 (SCR0)
Serial input register/serial output register 0 (SIDR/SODR0)
Asynchronous : 9615 bps, 31250 bps, 4808 bps, 2404 bps and 1202 bps
CLK synchronous : 1 Mbps, 500 kbps, 250 kbps, 125 kbps, 115.2 kbps and 62.5 kbps
Address : 000020
Address : 000021
Address : 000022
Address : 000023
Address : 000027
R/W
bit 15
W
—
R
X
: Readable and writable
: Read only
: Write only
: Unused
: Indeterminate
CDCR
8 bits
SCR
SSR
H
H
H
H
H
bit 15
bit 15
bit 15
MD1
R/W
PEN
R/W
R/W
R/W
bit 7
bit 7
MD
D7
PE
R
bit 8 bit 7
bit 14
bit 14
bit 14
MD0
R/W
ORE
R/W
R/W
bit 6
bit 6
D6
—
—
P
R
bit 13
bit 13
bit 13
R/W
SIDR (R) /SODR (W)
CS2
R/W
SBL
FRE
bit 5
bit 5
R/W
D5
—
R
—
RDRF TDRE
bit 12
bit 12
bit 12
8 bits
SMR
CS1
R/W
R/W
bit 4
bit 4
R/W
CL
D4
—
—
—
R
bit 11
bit 11
bit 11
DIV3
R/W
CS0 Reserved SCKE
R/W
R/W
bit 3
A/D
bit 3
R/W
D3
R
MB90650A Series
bit 10
REC
bit 10
bit 10
DIV2
R/W
bit 2
bit 2
R/W
R/W
D2
bit 0
—
—
W
For a 6, 8, 10, 12, or 16 MHz
clock.
DIV1
RXE
bit 1
R/W
bit 9
R/W
bit 1
bit 9
RIE
R
R/W
bit 9
R/W
R/W
D1
SOE
DIV0
TXE
R/W
R/W
R/W
bit 0
bit 8
bit 0
R/W
bit 8
bit 8
TIE
D0
R/W
0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0
XXXXXXXX
0 0 0 0 1 - 0 0
0 - - - 1 1 1 1
Initial value
Initial value
Initial value
Initial value
Initial value
B
B
B
B
B
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