X4163 INTERSIL [Intersil Corporation], X4163 Datasheet - Page 12

• Manufacturer Part Number: X4163
• Description: CPU Supervisor with 16K EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

Figure 14. Sequential Read Sequence
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1.
The address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to address 0000
to output data for each acknowledge received. Refer
to Figure 14 for the acknowledge and data transfer
sequence.
Signals from
Signals from
the Slave
the Master
SDA Bus
12
H
Address
Slave
and the device continues
1
A
C
K
Data
(1)
X4163, X4165
A
C
K
Data
(2)
X4163/5 Addressing
S
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several
parts:
– a device type identifier that is ‘1010’ to access the
– one bits of ‘0’.
– next two bits are the device address.
– one bit of the slave command byte is a R/W bit. The
– After loading the entire Slave Address Byte from the
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
LAVE
array.
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 15.
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
A
C
A
K
DDRESS
(n is any integer greater than 1)
Data
(n-1)
B
YTE
A
C
K
Data
(n)
April 13, 2005
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FN8120.0