X4163 INTERSIL [Intersil Corporation], X4163 Datasheet - Page 2

• Manufacturer Part Number: X4163
• Description: CPU Supervisor with 16K EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

PIN CONFIGURATION
PIN FUNCTION
(SOIC)
Pin
1
2
3
4
5
6
7
8
RESET/RESET
(TSSOP)
Pin
3
4
5
6
7
8
1
2
V
V
WP
CC
S
S
S
S
SS
0
1
0
1
8-Pin JEDEC SOIC
8 Pin TSSOP
1
2
3
4
1
2
3
4
RESET /
RESET
Name
SDA
SCL
V
V
WP
S
S
2
CC
SS
0
1
8
7
6
5
8
7
6
5
SCL
SDA
V
WP
SCL
SDA
V
RESET/RESET
CC
SS
Device Select Input
Device Select Input
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
active until V
RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains
either HIGH or LOW longer than the selectable Watchdog time out period. A falling
edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET
goes active on power up and remains active for 250ms after the power supply sta-
bilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
Supply Voltage
CC
X4163, X4165
rises above the minimum V
CC
falls below the minimum V
Function
CC
sense level for 250ms.
CC
sense level. It will remain
April 13, 2005
FN8120.0