71M6545 MAXIM [Maxim Integrated Products], 71M6545 Datasheet - Page 40

• Manufacturer Part Number: 71M6545
• Description: Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size
• Manufacturer: MAXIM [Maxim Integrated Products]

Data Sheet 71M6545/H
2.4.9 WD Timer (Software Watchdog Timer)
There is no internal software watchdog timer. Use the standard hardware watchdog timer instead (see
2.5.13 Hardware Watchdog
2.4.10 Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own interrupt request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in IEN0 (SFR 0xA8), IEN1
(SFR 0xB8), and IEN2 (SFR 0x9A).
Referring to
Internal Sources) or can originate from other parts of the 71M6545/H Metrology Processor (referred to as
External Sources). There are seven external interrupt sources, as seen in the leftmost part of
and in
Interrupt Overview
When an interrupt occurs, the MPU vectors to the predetermined address as shown in
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service
is terminated by a return from instruction, RETI. When an RETI is performed, the processor returns to the
instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor also indicates this by setting a flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt when
the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt is
acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following conditions
are met:
•
•
•
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
•
•
•
•
40
TCON[4]
TCON[3]
TCON[2]
TCON[1]
TCON[0]
IEN0[7]
IEN0[6]
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
The interrupt enable registers: IEN0, IEN1 and IEN2 (see
The Timer/Counter control registers, TCON and T2CON (see
The interrupt request register, IRCON (see
The interrupt priority registers: IP0 and IP1 (see
Bit
Bit
Table 24
Figure 12,
Symbol
TR0
IE1
IT1
IE0
IT0
and
WDT
EAL
Symbol
Table 25
interrupt sources can originate from within the 80515 MPU core (referred to as
EAL = 0 disables all interrupts.
Not used for interrupt control.
© 2008–2011 Teridian Semiconductor Corporation
Timer).
Table 24: The IEN0 Bit Functions (SFR 0xA8)
(i.e., EX0-EX6).
Timer 0 Run control bit. If cleared, Timer 0 stops.
Interrupt 1 edge flag is set by hardware when the falling edge on external
pin int1 is observed. Cleared when an interrupt is processed.
Interrupt 1 type control bit. Selects either the falling edge or low level on
input pin to cause an interrupt.
Interrupt 0 edge flag is set by hardware when the falling edge on external
pin int0 is observed. Cleared when an interrupt is processed.
Interrupt 0 type control bit. Selects either the falling edge or low level on
input pin to cause interrupt.
Figure 12
shows the device interrupt structure.
Table
Table
29).
34).
Function
Table
Function
Table 27
24,
Table 25
and
Table
and
28).
Table
Table
PDS_6545_009
26).
36. Once
Figure
12,
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