71M6545 MAXIM [Maxim Integrated Products], 71M6545 Datasheet - Page 56

• Manufacturer Part Number: 71M6545
• Description: Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size
• Manufacturer: MAXIM [Maxim Integrated Products]

A 3-bit configuration word, I/O RAM register DIO_Rn[2:0] (I/O RAM 0x2009[2:0] through 0x200E[6:4]) can
Data Sheet 71M6545/H
The PB pin is a dedicated digital input and is not part of the DIO system.
be used for pins DIO2 through DIO11 (when configured as DIO) and PB to individually assign an internal
resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0], configures the PB
pin). This way, DIO pins can be tracked even if they are configured as outputs.
internal resources which can be assigned using DIO_R2[2:0] (also called DIO_RPB[2:0]) through
DIO_R11[2:0] and DIO_RPB[2:0]. If more than one input is connected to the same resource, the resources
are combined using a logical OR.
56
DIO
Pin #
DIO Data Register
Direction Register:
0 = input, 1 = output
The CE features pulse counting registers and the CE pulse outputs are directly routed to the
pulse interrupt input. Thus, no routing of pulse signals to external pins is required in order to
generate pulse interrupts.
When driving LEDs, relay coils etc., the DIO pins should sink
in
resistance of the internal switch that connects V3P3D to V3P3SYS.
Sourcing current in or out of DIO pins other than those dedicated for wake functions, for example
with pull-up or pull-down resistors, should be avoided. Violating this rule leads to increased
quiescent current from a battery connected to the VBAT_RTC pin during SLP mode.
Figure 14
Value in DIO_Rn[2:0]
DIO Data Register
Direction Register:
0 = input, 1 = output
Table 45: Data/Direction Registers for DIO19-25 and DIO28-29
Table 47: Selectable Resources using the DIO_Rn[2:0] Bits
, right), not
0
1
2
3
4
5
Pin #
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DIO
Table 46: Data/Direction Registers for DIO55
source it from V3P3D (as shown in
19
14
19
19
None
Reserved
T0 (counter0 clock)
T1 (counter1 clock)
High priority I/O interrupt (INT0)
Low priority I/O interrupt (INT1)
–
–
–
–
20
13
20
20
Resource Selected for DIOn or PB Pin
–
–
–
–
(I/O RAM 0x2420[0] to 0x242F[0])
(I/O RAM 0x2420[1] to 0x242F[1])
21
12
21
21
(I/O RAM 0x2443[0] to 0x2447[0])
(I/O RAM 0x2443[1] to 0x2447[1])
–
–
–
–
DIO16[0] to DIO31[0]
DIO16[1] to DIO31[1]
DIO51[0] to DIO55[0]
DIO51[1] to DIO55[1]
22
11
22
22
–
–
–
–
23
10
23
23
55
32
55
55
24
24
24
9
Figure 14
25
25
25
–
–
–
–
8
the current into GNDD (as shown
–
–
–
–
, left). This is due to the
Table 47
–
–
–
–
28
28
28
7
PDS_6545_009
lists the
29
29
29
6
v1.0