71M6545 MAXIM [Maxim Integrated Products], 71M6545 Datasheet - Page 61

• Manufacturer Part Number: 71M6545
• Description: Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size
• Manufacturer: MAXIM [Maxim Integrated Products]

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SPI Safe Mode
Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus
disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI
SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte
transfer region at address 0x400 to 0x40F. If the SPI host needs to write to other addresses, it must use
the SPI_CMD register to request the write operation from the MPU. SPI SAFE mode is enabled by the
SPI_SAFE bit (I/O RAM 0x270C[3]).
Single-Byte Transaction
If a transaction is a single byte, the byte is interpreted as SPI_CMD. Regardless of the byte value,
single-byte transactions always update the SPI_CMD register and cause an SPI interrupt to be generated.
Multi-Byte Transaction
As shown in
and a sequence of data bytes. A multi byte transaction is three or more bytes.
PDS_6545_009
The SPI_STAT byte is output on every SPI transaction and indicates the parity of the previous transaction
and the error status of the previous transaction. Potential error sources are:
v1.0
Command
(From Host) SPI_CSZ
(From Host) SPI_CSZ
(From 6545) SPI_DO
(From 6545) SPI_DO
Address
(From Host) SPI_CK
(From Host) SPI_CK
SERIAL READ
SERIAL WRITE
(From Host) SPI_DI
(From Host) SPI_DI
Status
Name
Field
Data
71M6545/H not ready
Transaction not ending on a byte boundary.
Figure
Yes, if transaction
Yes, if transaction
x
Figure 20: SPI Slave Port - Typical Multi-Byte Read and Write operations
includes DATA
includes DATA
Yes, except
transaction
single byte
A15
A15
Required
0
0
Yes
20, multi-byte operations consist of a 16 bit address field, an 8 bit CMD, a status byte,
A14
A14
16 bit Address
16 bit Address
A1
A1
© 2008–2011 Teridian Semiconductor Corporation
HI Z
HI Z
15
15
A0
A0
(bytes)
more
Size
16
16
1 or
C7
C7
2
1
1
Table 50: SPI Transaction Fields
C6
C6
8 bit CMD
8 bit CMD
C5
C5
Description
16-bit address. The address field is not required if the transaction
is a simple SPI command.
8-bit command. This byte can be used as a command to the
MPU. In multi-byte transactions, the MSB is the R/W bit. Unless
the transaction is multi-byte and SPI_CMD is exactly 0x80 or
0x00, the SPI_CMD register is updated and an SPI interrupt is
issued. Otherwise, the SPI_CMD register is unchanged and the
interrupt is not issued.
8-bit status field, indicating the status of the previous transaction.
This byte is also available in the MPU memory map as
SPI_STAT (I/O RAM 0x2708). See
The read or write data. Address is auto incremented for each
new byte.
23
23
C0
C0
ST7
ST7
24
24
ST6
ST6
Status Byte
Status Byte
ST5
ST5
ST0
ST0
31
31
D7
32
32
D7
x
D6
D6
DATA[ADDR]
DATA[ADDR]
Table 52
D1
D1
D0
D0
39
39
Data Sheet 71M6545/H
for the contents.
40
D7
40
D7
Extended Read . . .
Extended Write . . .
D6
D6
DATA[ADDR+1]
DATA[ADDR+1]
D1
D1
D0
D0
47
47
x
61