ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 12

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Timing Specifications (Cont.)
Boundary Scan Logic
JTAG Interface and Programming Mode
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MAX
CKH
CKL
ISPEN
ISPDIS
HVDIS
HVDIS
CEN
CDIS
SU1
H
CO
PWV
PWP
BEW
BTCP
BTCH
BTCL
BTSU
BTH
BRF
BTCO
BTOZ
BTVO
BVTCPSU
BTCPH
BTUCO
BTUOZ
BTUOV
Symbol
Symbol
Maximum TCK Clock Frequency
TCK Clock Pulse Width, High
TCK Clock Pulse Width, Low
Program Enable Delay Time
Program Disable Delay Time
High Voltage Discharge Time, Program
High Voltage Discharge Time, Erase
Falling Edge of TCK to TDO Active
Falling Edge of TCK to TDO Disable
Setup Time
Hold Time
Falling Edge of TCK to Valid Output
Verify Pulse Width
Programming Pulse Width
Bulk Erase Pulse Width
TCK (BSCAN Test) Clock Cycle
TCK (BSCAN Test) Pulse Width High
TCK (BSCAN Test) Pulse Width Low
TCK (BSCAN Test) Setup Time
TCK (BSCAN Test) Hold Time
TCK (BSCAN Test) Rise and Fall Rate
TAP Controller Falling Edge of Clock to Valid Output
TAP Controller Falling Edge of Clock to Data Output Disable
TAP Controller Falling Edge of Clock to Data Output Enable
BSCAN Test Capture Register Setup Time
BSCAN Test Capture Register Hold Time
BSCAN Test Update Register, Falling Edge of Clock to Valid Output
BSCAN Test Update Register, Falling Edge of Clock to Output Disable
BSCAN Test Update Register, Falling Edge of Clock to Output Enable
Parameter
Parameter
12
Condition
ispClock5500 Family Data Sheet
Min.
200
200
20
20
15
30
30
10
30
10
—
—
—
—
8
Min.
40
20
20
10
50
10
—
—
—
—
—
—
8
8
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
10
10
10
25
25
25
—
—
—
—
—
—
—
—
Max.
25
15
15
15
—
—
—
—
—
—
—
—
—
—
—
mV/ns
Units
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
µs
µs
µs
µs
ns
ns
ns
ns
ns
µs