ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 13

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Timing Diagrams
Figure 7. Erase (User Erase or Erase All) Timing Diagram
Figure 8. Programming Timing Diagram
Figure 9. Verify Timing Diagram
Figure 10. Discharge Timing Diagram
State
TCK
TMS
TMS
TCK
State
State
TCK
TMS
State
TCK
TMS
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIL
Update-IR
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIL
Update-IR
t
SU1
Update-IR
Update-IR
t
SU1
t
SU1
t
SU1
t
CKH
t
t
H
CKH
t
H
Run-Test/Idle (Erase or Program)
t
SU1
t
CKH
t
t
t
SU1
CKH
CKL
t
t
t
GKL
H
H
Run-Test/Idle (Erase)
t
SU1
t
SU1
t
t
CKL
CKL
t
H
Run-Test/Idle (Program)
Run-Test/Idle (Program)
t
H
The clock (TCK) must be
able to run free with TMS = VIL
t
PWP
The clock (TCK) must be
able to run free with TMS = VIL
The clock (TCK) must be
able to run free with TMS=VIL
t
t
t
H
H
or t
BEW
BEW
t
t
SU1
SU1
t
PWP
t
PWV
Select-DR Scan
t
Select-DR Scan
t
CKH
CKH
t
t
t
SU1
t
H
SU1
H
13
t
Select-DR Scan
Select-DR Scan
CKH
t
CKH
t
t
H
H
t
SU1
t
SU1
t
HVDIS
ispClock5500 Family Data Sheet
t
CKH
(Actual)
t
t
CKH
H
t
H
t
Run-Test/Idle (Discharge)
t
The clock (TCK) must be
able to run free with TMS = VIL
t
SU1
SU1
SU1
t
GKL
t
Run-Test/Idle (Verify)
SU1
t
CKL
t
Specified by the Data Sheet
CKH
t
t
t
CKH
CKH
H
t
Update-IR
Update-IR
Specified by the Data Sheet
CKH
t
t
H
H
t
H
t
SU2
t
t
SU1
SU1
t
t
PWV
t
CKL
CKL
t
SU1
t
Actual
SU1
t
PWV
t
t
CKH
CKH
t
t
H
t
H
CKH
t
H
t
CKH
t
H