GS88018AT-133 ETC, GS88018AT-133 Datasheet - Page 7

• Manufacturer Part Number: GS88018AT-133
• Description: 512K x 18/ 256K x 32/ 256K x 36 9Mb Sync Burst SRAMs
• Manufacturer: ETC

Mode Pin Functions
Note:
There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
Notes:
1.
2.
3.
4.
Rev: 1.02 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Byte Write Truth Table
2nd address
3rd address
1st address
4th address
Write all bytes
Write all bytes
All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
Byte Write Enable inputs B
All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Bytes “
Write byte a
Write byte b
Write byte c
Write byte d
Function
Read
Read
Power Down Control
Burst Order Control
Mode Name
C
” and “
D
A[1:0] A[1:0] A[1:0] A[1:0]
” are only available on the x32 and x36 versions.
00
01
10
11
GW
H
H
H
H
H
H
H
L
A
, B
01
10
00
11
B
, B
C
and/or B
Name
BW
10
11
00
01
LBO
H
Pin
L
L
L
L
L
L
X
ZZ
D
may be used in any combination with BW to write single or multiple bytes.
00
01
10
11
L or NC
State
H
H
L
B
H
X
H
H
H
X
L
L
A
7/26
B
Standby, I
I
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst
X
H
H
H
H
X
L
L
nterleaved Burst Sequence
B
Linear Burst
Function
2nd address
3rd address
4th address
1st address
Active
GS88018/32/36AT-250/225/200/166/150/133
DD
= I
B
X
H
H
H
H
X
L
L
SB
C
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
B
X
H
H
H
H
X
L
L
D
01
00
11
10
© 2001, Giga Semiconductor, Inc.
Notes
2, 3, 4
2, 3, 4
2, 3, 4
10
00
01
11
2, 3
2, 3
1
1
11
10
01
00
BPR 1999.05.18