GS820E32T GSI Technology, GS820E32T Datasheet

GS820E32T

Manufacturer Part Number

GS820E32T

Description

64K x 32 / 2M Synchronous Burst SRAM

Manufacturer

GSI Technology

Datasheet

1.GS820E32T.pdf (23 pages)

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TQFP, QFP

Commercial Temp

Industrial Temp

Features

• FT pin for user configurable flow through or pipelined operation.

• Dual Cycle Deselect (DCD) Operation.

• 3.3V +10%/-5% Core power supply

• 2.5V or 3.3V I/O supply.

• LBO pin for linear or interleaved burst mode.

• Internal input resistors on mode pins allow floating mode pins.

• Default to Interleaved Pipelined Mode.

• Byte write (BW) and/or global write (GW) operation.

• Common data inputs and data outputs.

• Clock Control, registered, address, data, and control.

• Internal Self-Timed Write cycle.

• Automatic power-down for portable applications.

• JEDEC standard 100-lead TQFP or QFP package.

Functional Description

Applications

The GS820E32 is a 2,097,152 bit high performance synchronous

SRAM with a 2 bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPU’s, the device now finds application in synchronous

SRAM applications ranging from DSP main store to networking chip

set support.

Controls

Addresses, data I/O’s, chip enables (E

inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are

synchronous and are controlled by a positive edge triggered clock

input (CK). Output enable (G) and power down control (ZZ) are

asynchronous inputs. Burst cycles can be initiated with either ADSP

or ADSC inputs. In Burst mode, subsequent burst addresses are

generated internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or interleave order

with the Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Rev: 1.03 2/2000

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

tCycle

270mA

170mA

10.5ns

6.6ns

3.8ns

-150

9ns

245mA

120mA

7.25ns

9.7ns

15ns

-138

4ns

2M Synchronous Burst SRAM

240mA

120mA

7.5ns

15ns

10ns

-133

4ns

, E

210mA

120mA

), address burst control

8.5ns

15ns

11ns

-117

4.5

180mA

120mA

10ns

15ns

12ns

-100

5ns

64K x 32

1/23

150mA

12.5ns

95mA

20ns

18ns

6ns

-66

Flow Through / Pipeline Reads

The function of the Data Output register can be controlled by the user

via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FP-

BGA). Holding the FT mode pin/bump low, places the RAM in Flow

through mode, causing output data to bypass the Data Output

activating the rising edge triggered Data Output Register.

DCD Pipelined Reads

The GS820E32 is a DCD (Dual Cycle Deselect) pipelined

synchronous SRAM. SCD (Single Cycle Deselect) versions are also

available. DCD SRAMs pipeline disable commands to the same

degree as read commands. DCD RAMs hold the deselect command

for one full cycle and then begin turning off their outputs just after the

second rising edge of clock.

Byte Write and Global Write

Byte write operation is performed by using byte write enable (BW)

input combined with one or more individual byte write signals (Bx). In

addition, Global Write (GW) is available for writing all bytes at one

time, regardless of the Byte Write control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of

the ZZ signal, or by stopping the clock (CK). Memory data is retained

during Sleep mode.

Core and Interface Voltages

The GS820E32 operates on a 3.3V power supply and all inputs/

outputs are 3.3V and 2.5V compatible. Separate output power (V

pins are used to de-couple output noise from the internal circuit.

GS820E32T/Q-150/138/133/117/100/66

150Mhz - 66Mhz

3.3V & 2.5V I/O

9ns - 18ns

3.3V VDD

DDQ

)

Related parts for GS820E32T

GS820E32T Summary of contents

Page 1

... The GS820E32 operates on a 3.3V power supply and all inputs/ outputs are 3.3V and 2.5V compatible. Separate output power (V pins are used to de-couple output noise from the internal circuit address burst control 3 1/23 GS820E32T/Q-150/138/133/117/100/66 150Mhz - 66Mhz 3.3V & 2.5V I/O © 1999, Giga Semiconductor, Inc. 9ns - 18ns 3.3V VDD ) ...

Page 2

... V DDQ Rev: 1.03 2/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS820E32T/Q-150/138/133/117/100/66 64K x 32 Top View 2/ ...

Page 3

... Flow Through or Pipeline mode. Active Low. LBO I Linear Burst Order mode. Active Low DDQ 3/23 GS820E32T/Q-150/138/133/117/100/66 Description Address Inputs Data Input and Output pins. No Connect , DQ Data I/O’s. Active Low Data I/O’s. Active Low Clock Input Signal. Active High. ...

Page 4

... Power Down ZZ Control Rev: 1.03 2/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS820E32T/Q-150/138/133/117/100/ Counter Load Register D Q Register D Q Register D Q Register D Q Register ...

Page 5

... Note: The burst counter wraps to initial state on the 5th clock may be used in any combination with BW to write single or multiple bytes. D 5/23 GS820E32T/Q-150/138/133/117/100/ A[1:0] A[1:0] A[1:0] A[1: Notes ...

Page 6

... X H None X L None Next CR X Next CR H Next CW X Next 6/23 GS820E32T/Q-150/138/133/117/100/66 ADSP ADSC ADV ...

Page 7

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. X Deselect First Write Burst Write 7/23 GS820E32T/Q-150/138/133/117/100/ First Read Burst Read CR ) and Write ( and GW) control inputs © 1999, Giga Semiconductor, Inc. ...

Page 8

... Data Input Set Up Time. Rev: 1.03 2/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. X Deselect First Write Burst Write 8/23 GS820E32T/Q-150/138/133/117/100/ First Read Burst Read CR © 1999, Giga Semiconductor, Inc. D ...

Page 9

... Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be -2V > Vi < V Rev: 1.03 2/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS820E32T/Q-150/138/133/117/100/66 Value -0.5 to 4 ...

Page 10

... Symbol Test conditions C V =3. = =0V OUT OUT Layer Board Symbol R single JA R four 10/23 GS820E32T/Q-150/138/133/117/100/66 20% tKC IL Typ. Max. Unit TQFP Max QFP Max Unit 40 TBD C/W 24 TBD C/W 9 TBD C/W © 1999, Giga Semiconductor, Inc. ...

Page 11

... -1uA 300uA -300uA 1uA -1uA 1uA Output Disable, -1uA 1uA OUT 4mA, V =2.375V 1.7V DDQ = - 4mA, V =3.135V 2.4V DDQ I = 4mA 0.4V OL 11/23 GS820E32T/Q-150/138/133/117/100/66 Output Load 2 2.5V 225 DQ * 225 5pF © 1999, Giga Semiconductor, Inc. D ...

Page 12

... Pipeline 120mA 125mA Flow-Thru I SB 10mA Flow-Thru I DD 70mA Pipeline I DD 40mA IL Flow-Thru 12/23 GS820E32T/Q-150/138/133/117/100/66 -138 - 70°C - 70°C 85°C 85°C 245mA 250mA 240mA 120mA 125mA 120mA 15mA 10mA 15mA 10mA 95mA 80mA 85mA 80mA 50mA ...

Page 13

... GS820E32T/Q-150/138/133/117/100/66 -133 -117 -100 Max Min Max Min Max Min --- 8.5 --- 10 12.5 4 --- 4.5 5 --- 2 --- 2 2 --- 2 --- 2 2 --- 15 --- --- 11 12 --- 3 --- 3 3 --- 3 --- 3 3 --- 2 --- 3 4 --- 2 --- ...

Page 14

... WR2 1 E masks ADSP and E only sampled with ADSP or ADSC tS tH Write specified byte for 14/23 GS820E32T/Q-150/138/133/117/100/66 Deselected Write 1 inactive ADSC initiated write WR3 WR3 WR3 Deselected with and all bytes for & ...

Page 15

... E masks ADSP and E only sampled with ADSP or ADSC tOHZ tOE tKQX 15/23 GS820E32T/Q-150/138/133/117/100/66 1 inactive ADSC initiated read Suspend Burst RD3 tH tH Deselected with E tKQX © 1999, Giga Semiconductor, Inc. 2 tHZ D ...

Page 16

... WR1 E2 and E3 only sampled with ADSP and ADSC tOHZ 16/23 GS820E32T/Q-150/138/133/117/100/66 Burst Read ADSP is blocked by E inactive E1 masks ADSP Deselected with Burst wrap around to it’s initial state © 1999, Giga Semiconductor, Inc. ...

Page 17

... Suspend Burst RD2 and E only sampled with ADSP or ADSC tOE tOHZ tKQX tOLZ A Q1a Q2 tLZ tKQ 17/23 GS820E32T/Q-150/138/133/117/100/66 1 inactive ADSC initiated read RD3 masks ADSP Deselected with © 1999, Giga Semiconductor, Inc. 2 tKQX ...

Page 18

... ADSC initiated read RD2 WR1 WR1 and E only sampled with ADSP and ADSC tOE tOHZ tS tH tKQ A Q1 D1A 18/23 GS820E32T/Q-150/138/133/117/100/66 Burst Read 1 inactive 1 E masks ADSP Deselected with © 1999, Giga Semiconductor, Inc ...

Page 19

... Rev: 1.03 2/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tKC tKH tKL tZZH tZZS Snooze 19/23 GS820E32T/Q-150/138/133/117/100/66 tZZR © 1999, Giga Semiconductor, Inc. D ...

Page 20

... Rev: 1.03 2/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Out (Pull Down) VDDQ - V Out (Pull Up 20/23 GS820E32T/Q-150/138/133/117/100/66 VDDQ I Out VOut VSS 2.5 3 3 © 1999, Giga Semiconductor, Inc ...

Page 21

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com TQFP Min. Nom. Max Standoff 0.05 0.10 0.15 1.35 1.40 1.45 Lead Width 0.20 0.30 0.40 0.09 0.20 21.9 22.0 22.1 19.9 20.0 20.1 15.9 16.0 16.1 13.9 14.0 14.1 Lead Pitch 0.65 Foot Length 0.45 0.60 0.75 Lead Length 1.00 Coplanarity 0.10 Lead Angle 0 7 21/23 GS820E32T/Q-150/138/133/117/100/66 QFP Min. Nom. Max 0.25 0.35 0.45 2.55 2.72 2.90 0.20 0.30 0.40 0.10 0.15 0.20 22.95 23.2 23.45 19.9 20.0 20.1 17.0 17.2 17.4 13.9 14.0 14.1 0.65 .60 0.80 1.00 1.60 0. © 1999, Giga Semiconductor, Inc. D ...

Page 22

... Pipeline/Flow Through Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS820E32T-100IT. 2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline / Flow through mode selectable by the user ...

Page 23

... Ordering information. Changed “0” before “H” or “E” in part number. Content • Ordering information. Changed - 117 to -4, -100 to -5. and -66 to -6. • New GSI Logo • Switched TKQ with TCycle in Flow Through part of table on page 1. Format/Content 23/23 GS820E32T/Q-150/138/133/117/100/66 © 1999, Giga Semiconductor, Inc. D ...

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