CDP1854 Intersil Corporation, CDP1854 Datasheet - Page 20

• Manufacturer Part Number: CDP1854
• Description: Programmable Universal Asynchronous Receiver/Transmitter (UART)
• Manufacturer: Intersil Corporation

NOTES:
NOTES:
1. The holding register is loaded on the trailing edge of THRL.
2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + t
1. If a start bit occurs at a time less than t
2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding
after the trailing edge of THRL and transmission of a start bit occurs 1/2 clock period + t
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
register, the OE signal will come true.
R CLOCK
R BUS 0 -
(NOTE 2)
R BUS 7
START BIT
DAR
T CLOCK
SDI
T BUS 0
T BUS 7
DA
OE
PE
FE
(NOTE 1)
t
THRE
CH
THRL
TSRE
SDO
t
DC
t
CC
t
CL
1
t
CH
2
t
THC
t
t
FIGURE 10. MODE 0 TRANSMITTER TIMING DIAGRAM
t
TTHR
THTH
CC
t
FIGURE 11. MODE 0 RECEIVER TIMING DIAGRAM
DC
DT
3
START BIT
t
DATA
DATA
CL
before a high-to-low transition of the clock, the start bit may not be recognized until the next
LSB
FIGURE 12. SERIAL DATA WORD FORMAT
4
5 - 8 DATA BITS
CDP1854A, CDP1854AC
CLOCK 7 1/2
t
TD
SAMPLE
5
t
t
DDA
DD
1
16 / f
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
t
6
TTS
PARITY
2
DATA
CLOCK
MSB
t
CD
t
7
CT
5-61
3
16
4
STOP BIT 1
1
5
2
6
PARITY BIT
HOLDING REGISTER
3
CLOCK 7 1/2 LOAD
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
7
CD
4
14
later.
5
15
NEXT DATA WORD
STOP BITS 1, 1-1/2 OR 2
t
COE
6
t
t
CPE
16
CFE
7
1
1ST DATA BIT
8
2
t
CD
9
t
t
CDA
CDV
3
THC