PSB4596 Siemens Semiconductor Group, PSB4596 Datasheet
PSB4596
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PSB4596 Summary of contents
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ICs for Communications Analog Line Interface Solution ALIS PSB 4595 Version 2.1 PSB 4596 Version 2.1 Data Sheet 06. ...
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ALIS Revision History: Previous Version: Page Page Subjects (major changes since last revision) (in previous (in new Version) Version) Edition 06.98 This edition was realized using the software system FrameMaker . Published by Siemens AG © Siemens AG ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 6.1 Types of Commands and Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 ...
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Table of Contents 8.1.3 Interrupt Indication at High Level ...
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Table of Contents 11.3.1 Ringer Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview The PSB 4595 and PSB 4596 two-chip solution forms the complete front end of a modem or fax machine. This Analog Line Interface Solution (ALIS) consists of a DAA, a codec and a hybrid circuit, and bridges the ...
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Analog Line Interface Solution ALIS 1.1 Features • ALIS substitutes data access arrangement (DAA), codec and hybrid • Ring detection: level, frequency and cadence • Caller ID: detection, decoding and storage • Programmable to different country requirements • Programmable DC ...
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Logic Symbol MCLK RESET Data Interface ALIS-D C Interface SO Figure 1 Logic Symbol of the ALIS Chipset Semiconductor Group Analog Line Interface Solution Isolation Vdd Vss Cap ALIS _A ALIS-A Interface Caller ID Interface 9 PSB 4595 / ...
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Pin Definition and Functions 2.1 Pin Configuration CAP1 CAP2 VREF TIP TIP_AC RING RING_AC SO_0 SO_1Q CAP_B22 CAP_B21 CAP_A22 Figure 2 Pin Configuration of ALIS-A (Top View) CAP_A12 CAP_B11 CAP_B12 ID_Ain Afeedback ID_Bin Bfeedback VDD GND CS DCLK DIN ...
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Pin Definition of ALIS-A PSB 4595 Pin No. Symbol 22 VDDA 24 GNDA 4 TIP 5 TIP_AC 6 RING 7 RING_AC 23 T1G 19 T2G 21 VDD_SENS 3 VREF 1 CAP1 2 CAP2 18 SI_0 17 SI_1 8 SO_0 ...
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Pin No. Symbol 15 CAP_C21 14 CAP_C22 Table 1: ALIS-A Pin Definition Semiconductor Group Analog Line Interface Solution Function Descriptions I Must be connected via a capacitor of more than 5pF to CAP_C11. I Must be connected via a capacitor ...
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Pin Definition of ALIS-D PSB 4596 Pin No. Symbol 8 VDD 9 GND 25 VDDA 24 GNDA 21 MCLK1 20 MCLK2 23 RESET 15 FSC 17 DAT_IN / SEL 16 DAT_OUT 18 DAT_CLK 10 CS Semiconductor Group Analog Line ...
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Pin No. Symbol 11 DCLK 12 DIN 13 DOUT 14 INT 19 MODE 4 ID_Ain 6 ID_Bin 5 A feedback 7 B feedback 28 CAP_A11 1 CAP_A12 2 CAP_B11 3 CAP_B12 26 CAP_C11 27 CAP_C12 22 SO Table 2: ALIS-D ...
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System Integration ALIS can be used in different modem applications to connect the data pump to the TIP/ RING wire. 3.1 ALIS with DSP-based Modem For a modem data pump, the ALIS provides the front-end to the tip/ring. Data ...
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ALIS with Software Modem ALIS also supports software modems where V.34 runs on the host computer (e.g. in combination with a USB controller). ALIS-D PSB 4596 Microcontroller with USB or PCI Interface Figure 5 Software Modem Application Semiconductor Group ...
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Hybrid Modem (ISDN plus Analog) In combination with the SIEMENS ISDN chip set, ALIS supports hybrid modems, , allowing connection to either the TIP/RING line U-interface for ISDN applications. ALIS-D PSB 4596 Flash SRAM ...
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Modem with Speakerphone ALIS-D PSB 4596 Flash SI SRAM ISAR34 PSB 7115 Microcontroller with USB or V.24 Interface Figure 7 Application with Speakerphone: ARCOFI-SP Audio Ringing Codec (PSB 2160, PSB 2163, PSB 2165, PSB 2168) and ISAR34 Enhanced Data ...
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Analog Videophone The diagram below shows a system solution for an analog videophone application using a SIEMENS chip set. ALIS-D PSB 4596 Flash SRAM ISAR34 PSB 7115 Microcontroller with USB or V.24 Interface Figure 8 ARCOFI-(SP) Audio Ringing Codec ...
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ALIS Implementation The ALIS chip set replaces all the major parts of a conventional front end for modem solutions. The circuit consists of two major parts, a DSP-based codec and an electronic DAA. Advanced features such as ring detection, ...
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RAM (CRAM) in order to program the filters. Transmit and receive data is transferred to and from the data pump via the data interface. 4.2 ALIS AC Signal Flow Graph ALIS architecture is based on digital filters. The ...
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Receive Path After passing the DAA and a simple anti-aliasing pre-filter with an analog gain stage, the voice signal is converted to a 1-bit digital data stream in the sigma-delta converter. The first down-sampling steps are performed in fast ...
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ALIS Ring and Caller ID Signal Flow Graph CID out CIDL comparator for CID user-programmable block Figure 11 Ring Signal Flow Graph These data paths operate only when the ALIS is in Ringing state. 4.3.1 Caller ID (CID) Path ...
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Ring-Level Metering (RLM) Path The analog signal is converted to a 1-bit data stream in the ADC. After decimation in hardware filters, the remaining processing is done in the digital filter structure (in RLM): bandpass filtering to select the ...
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Configuration Overview 5.1 Connection to the Telephone Line VDDA SENS VDD T2G - TIP AC TIP T1G RING-AC RING VREF GNDA CAP1 CAP2 Figure 12 Connection of ALIS-A to the Telephone Line As shown in the figure, ALIS-A requires ...
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Two transistors (T1, T2) to handle the line current. T2 must be of depletion type, in order to deal with start-up. Recommended transistors: T1: SIEMENS BSP 88; T2: SIEMENS BSP 129. - Components for EMC protection: not shown, as ...
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CS DCLK DIN Control DOUT Figure 13 Example of a Write Access, two Data Bytes transferred If the first eight bits received via DIN specify a read command, ALIS will start to respond via DOUT with ...
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The data transfer is synchronized by DCLK. DIN is latched at the falling edge of DCLK, while DOUT changes with the rising edge of DCLK. During the execution of a command which is followed by output data (read command), the ...
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FSC DAT_CLK DAT_IN DAT_OUT Figure 16 Example of a Clock Rate higher than 128 kb/s The data package must stay within the frame, t The FSC signal can be generated externally by the host or by ALIS. Semiconductor Group Analog ...
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Interface Modes 5.2.3.1 Demux Mode Connection of the MODE pin to GND allows the µC and the data interface to be accessed via two serial ports. DSP (Data Pump) Figure 17 Host Interface in Demux Mode, FSC as Input ...
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Multiplex Mode Connection of the MODE pin to VDD allows the two interfaces to be time-multiplexed on a single port. The interfaces are selected by the DAT_IN/SEL pin. DSP (Data Pump) Figure 19 Host Interface in MUX Mode, FSC ...
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DSP (Data Pump) Figure 20 Host Interface in MUX mode, FSC as Output DAT_IN / SEL = 0 PIN No Function 11 DCLK DIN 13 DOUT 15 FSC (output) 1) must be connected to a fixed potential ...
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Figure 21 Protocol for Transmission of µC- and PCM Data in MUX Mode 5.3 Clocking ALIS operates with a typical master clock frequency of 16.384 MHz. This clock can either be supplied from an external source or generated with a ...
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Crystal clock Because ALIS includes an on-chip oscillator circuit, an external crystal may be used. This crystal is connected across the MCLK1 and MCLK2 pins with two capacitors (see Figure 22 ”External Crystal Connections” The CLK_EXT bit ...
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Capacitor Interface A capacitor interface is used to decouple ALIS-A from ALIS- bi-directional serial interface and is used for exchanging control and data information between ALIS-A and ALIS-D. The transmission format is digital to avoid distortion ...
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Caller ID Interface To receive the caller ID, ALIS-D must be connected to the line via an RC network. See the section “ALIS Caller ID Interface” on page 86". Figure 24 Caller ID Interface Connection of ALIS-D to Tip/Ring ...
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Programming ALIS Appropriate commands via the serial µ-controller interface enable very flexible programming and verification of ALIS. Four different commands are used to access the various control registers and RAMs: SOP (see page 38), XOP (see page 44), COP ...
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Storage of Programming Information: • 6 Configuration registers: • 8 Extended registers: • 1 Coefficient RAM: • 1 Caller ID RAM: 6.2 SOP Command The SOP (status operation) command allows the ALIS status registers to be written or read ...
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CR0 Configuration Register 0 (Filters) Default value: 00H Configuration register CR0 defines the basic ALIS settings, which are: enabling/ disabling the programmable digital filters and tone generators. Bit Enable Trans-Hybrid Balancing (TH)-Filter TH = ...
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CR1 Configuration Register 1 (Dialing) Default value: 00H Configuration register CR01 selects tone generator modes and other operating modes Bit Tone2 Tone1 E_Tone2 Enable programmable tone generator 2 E_Tone2= 0: Programmable tone generator 2 disabled ...
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Ringing metering function disabled Ringing metering function enabled 6.2.3 CR2 Configuration Register 2 (Caller ID) Bit 7 6 COT/R Default value: 00H COT/R Select cut-off transmit/receive paths Normal operation 0 0 ...
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Call_II = 0: 2nd tone of caller ID not detected 6.2.4 CR3 Configuration Register 3 (Test Loops) Bit 7 6 Test Loops Default value: 00H Test Loops Four-bit field for selection of analog and digital loopbacks 0101 ALB_CIF: Cap. interface ...
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CR4 Configuration Register 4 (Analog Gain) Bit 7 6 AGR_ AGR_ Default value: 00H AGR_Z Analog gain in impedance loop (can be used as AGC) AGR_Z = 00: Analog gain A disabled (0 dB amplification) ...
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CR5 Configuration Register 5 (Version) Bit 7 6 V_7 V_6 V The current version of ALIS (this byte cannot be written) 02H for ALIS V2.1 6.3 XOP Command The ALIS digital command/indication interface to the line and external equipment ...
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For XOP Read Commands Bit Wake_ up Default value: 00H Wake_up Wake_up Interrupt Wake_up = 0: No Wake_up Interrupt Wake_up = 1: If CLK_OFF bit is set (see “XR6 Extended Register 6 (Power State)” on page 49) ...
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SI_0 Status of pin SI_0 at ALIS-A is transferred to this register SI_1 Status of pin SI_1 at ALIS-A is transferred to this register Note: The auxiliary pins (SO_0, SO_1, SI_0, SI_1) are isolated via the capacitor interface. With XOP-Write ...
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M_Caller_ID = 0:Disable Caller_ID Interrupt M_Caller_ID = 1:Enable Caller_ID Interrupt M_VDD_OK M_VDD_OK = 0:Disable VDD Interrupt M_VDD_OK = 1:Enable VDD Interrupt M_SI_1 M_SI_1 = 0: Disable SI_1 Interrupts M_SI_1 = 1: Enable SI_1 Interrupts M_SI_0 M_SI_0 = 0: Disable SI_0 ...
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B_off = 0: Analog trans-hybrid filter on B_off = 1: Analog trans-hybrid filter off Note: The analog trans-hybrid filter is an analog pre-filter optimized for long loops with a trans-hybrid loss of about 10 dB. DCU = 00: U0 for ...
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XR5 Extended Register 5 (Ring Timer) Bit 7 6 T_7 T_6 Default value: 22H T ms Ring latency timer, programmable in steps ALIS-A decodes any signal of more than TIP/RING. This signal will ...
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Note: When a crystal is used, it will be turned off automatically when the CLK_OFF bit is set. It will be switched on when the CS signal goes low. However, the user must wait until the crystal is working before ...
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IM filter coefficients (part Ringer impedance (part FRR filter coefficients FRX filter coefficients filter coefficients 1 0 ...
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Register Summary 6.6.1 CR Registers: Bit 7 6 CR0 TH IM CR1 E_ E_ Tone2 Tone1 CR2 COT/R CR3 TestLoops CR4 AGR_ AGR_ CR5 V_7 V_6 Table 5: Summary of CR Registers 6.6.2 XR Registers: ...
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ALIS Command Structure The sections below show the structure of the SOP, XOP, COP and CAO write and read commands. Section 7.5 shows an example of a mixed command. 7.1 SOP Commands 7.1.1 SOP - Write Commands DIN 7 ...
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SOP - Read Commands DIN Bit SOP read 1 byte DIN Bit SOP read 2 ...
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XOP Commands 7.2.1 XOP - Write Commands DIN Bit XOP write 2 bytes XR1 XR0 DIN ...
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COP Command 7.3.1 COP - Write Commands DIN Bit COP write 4 bytes Coeff. 3 Coeff. 2 Coeff. 1 Coeff. 0 DIN 7 ...
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COP - Read Commands DIN Bit COP read 4 bytes DIN Bit COP read 8 ...
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CAO Command 7.4.1 CAO - Write Commands DIN Bit CAO write Caller ID 512 Caller ID 511 Caller ID 510 7.4.2 CAO - ...
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Example of a Mixed Command Every single command must begin with a falling edge of CS. DIN Bit SOP write 4 bytes CR3 ...
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Interrupt Controller There are seven different sources that can cause interrupts in ALIS. The status of these sources are read from interrupt register XR0. Every interrupt source can be enabled individually in interrupt-enable register XR1. To monitor an interrupt ...
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Interrupt Indication at Signal Change: Interrupts: Sources: Interrupt indication: Note: Lock behaviour: 8.1.2 Interrupt Indication at Event: Interrupts: Sources: Interrupt indication: Lock behaviour: Semiconductor Group SI_0, SI_1, VDD_OK; Signaling pins at ALIS-A (SI_0, SI_1); VDD_OK indicates that ALIS-A has ...
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Interrupt Indication at High Level: If ALIS-D is set to deep-sleep mode (XR6, CLK_OFF = ’1’), this interrupt indicates that there is a signal greater than TIP/RING. Interrupts: Source: Interrupt indication: Lock behaviour: Semiconductor Group WAKE_UP; ...
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Operating Modes 9.1 Reset (Basic Settings Mode) Condition: RESET low, MCLK can be down ALIS-D: After initial application of VDD (power-on reset), reset of the setting pin to ’0’ during operation or a software reset (see XOP command), ALIS-D ...
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Conversation Mode Condition: RESET ’1’, if used the external master clock must be activated. The operating mode is entered upon recognition of the PU bits set to '10 SOP command. In conversation mode, the AC impedance loops ...
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Operating Flowchart first ring ends & no caller valid ring on hook PULSE DIALING off hook user has to programm clock_off bit and supply clock signal in case of external clock 1 after this interrupts the ...
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XR6 (see “XR6 Extended Register 6 (Power State)” on page 49 second step, only if enabled by RM (see “CR1 Configuration Register 1 (Dialing)” on page 40) in ringing mode, the TIP/RING signal ...
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Successful Ring Sequence, Auto Ring Enabled, no Caller ID The following chart and diagram show the successful flow of a ring-event detection with automatic power-mode change (No_auto_ring = 0, Caller_en = 1). In this operating mode, ...
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Successful Ring Sequence, Auto Ring Enabled, Caller ID The following chart and diagram show the successful flow of a ring-event detection with automatic power-mode change (No_auto_ring = 0, Caller_en = 1). In this operating mode, ALIS ...
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Unsuccessful Ring Sequence, Auto Ring Enabled, no Caller ID The following chart and diagram show the unsuccessful flow of a ring-event detection because of no 2nd ring with automatic power-mode change (No_auto_ring = 0, Caller_en = ...
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Unsuccessful Ring Sequence, Auto Ring Enabled, Caller ID The following chart and diagram show the unsuccessful flow of a ring-event detection because of no 2nd ring with automatic power-mode change (No_auto_ring = 0, Caller_en = 1). ...
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Successful Ring Sequence, Auto Ring Disabled, No Caller ID The following chart and diagram show the successful flow of a ring-event detection with no automatic power-mode change (No_auto_ring = 1, Caller_en = 1). In this operating ...
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Successful Ring Sequence, Auto Ring Disabled, Caller ID The following chart and diagram show the successful flow of a ring-event detection with no automatic power-mode change (No_auto_ring = 1, Caller_en = 1). In this operating mode, ...
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Unsuccessful Ring Sequence, Auto Ring Disabled, no Caller ID The following chart and diagram show the unsuccessful flow of a ring-event detection because of no 2nd ring with no automatic power-mode change (No_auto_ring = 1, Caller_en = 0, RM ...
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Unsuccessful Ring Sequence, Auto Ring Disabled, Caller ID The following chart and diagram show the unsuccessful flow of a ring-event detection because of no 2nd ring with no automatic power-mode change (No_auto_ring = 0, Caller_en = ...
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Unsuccessful Ring Sequence, Auto Ring Enabled The following chart and diagram shows an unsuccessful flow of a ring-event detection because ringing is below the ring threshold level with an automatic power-mode change (No_auto_ring = 1). Line: ...
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Unsuccessful Ring Sequence, Auto Ring Disabled The following chart and diagram show an unsuccessful flow of a ring-event detection because ringing is below the ring threshold level with no automatic power-mode change (No_auto_ring = 1). Line: ...
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Start from Deep Sleep Mode The following chart and diagram show a start-up procedure from deep sleep mode. Line: on 1st ring hook Mode: deep sleep Interrupt: Wake_up Host CMDs: Figure 36 Deep Sleep Start Note: After the wake_up ...
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Modem Functions 10.1 Pulse Dialing Pulse dialing will be implemented by shortening the line with external transistor T1. Pulse timing must be controlled by the host. Pulse shaping is implemented in ALIS-A and complies with ETS 300 001 10.2 ...
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Table 7: Programming the tone generators The sine wave is filtered by a bandpass, the Q factor of this band filter can be ...
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Storage and Reading of Caller ID The storage of the decoded caller ID is enabled after the first space following the mark state. This event will be indicated by the caller ID interrupt. The maximum storage size is 4096 ...
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Programming the Frequency Command BELL 202 / 0E (CID1) CCITT V.23 0F (CID2) Table 9: Programming the ALIS Caller ID Coefficients 10.4 Billing Pulse Billing pulse frequencies of 12 and 16 kHz are filtered out by the digital part ...
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Programming the ALIS Ring Detect Coefficients Frequency Command 70Vrms Command 1 Table 10: Programming ALIS Ring Detect Coefficients Frequency Command 50Vrms Command 10k 03 0 Table ...
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Electrical Characteristics 11.1 Programmable Filters A set of programmable filters is used to adapt the whole system to: • country standards • board designs (EMI capacitors etc.) • data pumps • telephone lines Note: All these coefficients will be ...
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DC Termination The DC termination is enabled in conversation mode and is disabled during ringing mode, puls dialing mode and sleep mode. The DC termination can be programmed according to the formula: for i < Imax u Uo – ...
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Input Current in Puls Dialing Mode Uab = Parameter Input current at break Table 16: Input Current in Puls Dialing Mode 11.3 AC Termination 11.3.1 Ringer Impedance Programming of the ringer impedance is supported by a ...
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ALIS Caller ID Interface Parameter Capacitance Rin Rfb Table 18: ALIS Caller ID Interface 11.4.1 Ring Detect Levels and Frequencies . Parameter Range of programs for ring-level detection Ring-level detection step size Range of programs for frequency detection Table ...
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Electrical Performance Characteristic 12.1 Absolute Maximum Ratings Parameter Digital supply voltage Analog supply voltage Analog input and output voltage Digital input voltages DC input and output current Storage temperature Ambient temperature under bias Max. power dissipation Note: Stresses above ...
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Recommended Operating Conditions Parameter Digital supply voltage Analog supply voltage ALIS-A (programmed to 4.25 V) Analog supply voltage ALIS-D Ambient temperature under bias Operating frequency Clock duty cycle Signal rise and fall time Note: Extended operation outside the recommended ...
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Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Input current low Input current high Input resistance Sleep mode Conversation mode Pulse dialing mode Ring threshold Power supply rejection either supply/direction either supply/direction 1) Will be taken ...
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ALIS-D VDD = VDDA= 5V± 5%; TA=0 - 70°C Parameter Supply current Deep sleep mode Sleep mode Ringing mode Conversation mode Pulse dialing mode Low-level input voltage High-level input voltage VIH1 Low-level output voltage High-level output voltage Input current ...
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AC Transmission Characteristics Unless otherwise stated, the transmission characteristics are guaranteed within the following test conditions: TA=0 ° °C VDD=5V ±5% VDDA=4.25V (generated from ALIS-A) Line impedance ZL = 600 0.1% Ohms Termination impedance ZM = 600 ...
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Table 25: Absolute gain error 12.4.2 Gain Tracking AGX=AGR=0dB Parameter Gain tracking receive Gain tracking transmit Table 26: Gain Tracking 12.4.3 Harmonic Distortion plus Noise -10 dBm0; ZL= 600 f=1004 Hz Parameter HDN receive HDN transmit HDN receive HDN transmit ...
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Harmonic Distortion -10 dBm0; ZL= 600 f=100 to 2000 Hz, 2nd and 3rd harmonic Parameter HD receive HDN_R HD transmit HDN_T HD of echo signals HDN_E via TIP/RING Table 28: Harmonic Distortion for Echo Signals 12.4.5 Return Loss The ...
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Frequency Response 12.4.6.1 Receive Reference frequency 1kHz, input signal level 0dBm0 Figure 38 Frequency Response Receive Semiconductor Group PSB 4595 / PSB 4596 Analog Line Interface Solution Electrical Performance Characteristic 94 Data Sheet 06.98 ...
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Transmit Reference frequency 1kHz, input signal level 0dBm0 Figure 39 Frequency Response Transmit Semiconductor Group PSB 4595 / PSB 4596 Analog Line Interface Solution Electrical Performance Characteristic 95 Data Sheet 06.98 ...
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Group Delay Maximum delays when ALIS is operating with H(TH)=H(IM)=0 and H(FRR)=H(FRX)=1 including the delay through A/D- and D/A converters. Specific filter programming may cause additional group delays. Group Delay deviations remain within the limits in the figures below. ...
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Group Delay Distortion Transmit Input signal level 0dBm0 Figure 41 Group Delay Distortion Transmit switched on: reference point is at TGmin HPR is switched off: reference point is at 1.5 kHz Semiconductor Group Electrical Performance Characteristic ...
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Out-of-Band Signals at TIP/RING Receive When an 0dBm0 out-of-band sine-wave signal with a frequency of (<<100Hz or 3.4kHz to 100kHz) is applied to the analog input, the level of any resulting frequency component at the digital output will stay ...
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Out-of-Band Signals at TIP/RING Transmit When a 0 dBm0 sine wave with a frequency of (300Hz to 3.99kHz) is applied to the digital input, the level of any resulting out-of-band signal at the analog output will stay at least ...
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Trans-hybrid Loss The quality of trans-hybrid balancing is very sensitive to deviations in gain and group delay. These deviations are inherent in ALIS A/D and D/A converters as well as in all the external components used. Measurement of ALIS ...
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AC Timing Characteristics 12.5.1 Input/ Output Waveform for AC Tests 2,8 2,4 Test Points 0,8 0,4 Figure 44 Waveform for AC Tests 12.5.2 Reset Timing For resetting ALIS to its basic settings mode, negative pulses applied to the RESET ...
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VDD=VDDA= 5V± 5%; TA 70°C Parameter Clock cycle time Clock duty cycle Setup time, CS before DCLK Hold time, CS after DCLK Setup time, DIN before DCLK Hold time, DIN after DCLK Delay time, DCLK to DOUT Delay ...
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VDD=VDDA= 5V± 5%; TA=0 - 70°C Parameter Data clock cycle time Data clock duty cycle Frame synch clock cycle time FSC pulse width (as input) FSC pulse width (as output) Setup time, DAT_IN before DAT_CLK Hold time, DAT_IN after DAT_CLK ...
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Package Outlines P-SSOP28 (Plastic Shrink Small Outline Package) P-TSSOP24 (Plastic Thin Shrink Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group ...