AM28F020A-120EC AMD [Advanced Micro Devices], AM28F020A-120EC Datasheet - Page 12

• Manufacturer Part Number: AM28F020A-120EC
• Description: 2 Megabit (256 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
• Manufacturer: AMD [Advanced Micro Devices]

FLASH MEMORY PROGRAM/ERASE
OPERATIONS
Embedded Erase Algorithm
The automatic chip erase does not require the device
to be entirely pre-programmed prior to executing the
Embedded set-up erase command and Embedded
erase command. Upon executing the Embedded erase
command the device automatically will program and
verify the entire memory for an all zero data pattern.
The system is not required to provide any controls or
timing during these operations.
When the device is automatically verified to contain an
all zero pattern, a self-timed chip erase and verify be-
gin. The erase and verify operation are complete when
the data on DQ7 is “1" (see Write Operation Status sec-
tion) atwhich time the device returns to Read mode.
The system is not required to provide any control or
timing during these operations.
When using the Embedded Erase algorithm, the erase
automatically terminates when adequate erase margin
Note: See AC and DC Characteristics for values of V
switchable. When V
to Functional Description.
12
Standby
Write
Read
Standby
Read
Bus Operations
PP
is switched, V
Embedded Erase Setup Command
Embedded Erase Command
PPL
Command
may be ground, no connect with a resistor tied to ground, or less than V
Figure 1. Embedded Erase Algorithm
Table 4. Embedded Erase Algorithm
Write Embedded Erase Setup Command
Write Embedded Erase Command
Data# Poll from Device
PP
Erasure Completed
parameters. The V
Am28F020A
Apply V
START
Wait for V
Data = 30h
Data = 30h
Data
Compare Output to FFh
Available for Read Operations
PPH
has been achieved for the memory array (no erase ver-
ify command is required). The margin voltages are in-
ternally generated in the same manner as when the
standard erase verify command is used.
The Embedded Erase Set-Up command is a command
only operation that stages the device for automatic
electrical erasure of all bytes in the array. Embedded
Erase Setup is performed by writing 30h to the com-
mand register.
To commence automatic chip erase, the command 30h
must be written again to the command register. The au-
tomatic erase begins on the rising edge of the WE and
terminates when the data on DQ7 is “1" (see Write Op-
eration Status section) at which time the device returns
to Read mode.
Figure 1 and Table 4 illustrate the Embedded Erase al-
gorithm, a typical command string and bus operation.
#
Polling to Verify Erasure
PP
PP
Ramp to V
power supply can be hard-wired to the device or
PPH
Comments
(see Note)
CC
+ 2.0 V. Refer
17502D-6