AM28F020A-120EC AMD [Advanced Micro Devices], AM28F020A-120EC Datasheet - Page 8

• Manufacturer Part Number: AM28F020A-120EC
• Description: 2 Megabit (256 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
• Manufacturer: AMD [Advanced Micro Devices]

BASIC PRINCIPLES
The Am28FxxxA family uses 100% TTL-level control
inputs to manage the command register. Erase and
reprogramming operations use a fixed 12.0 V
high voltage input.
Read Only Memory
Without high V
read only memory and operates like a standard
EPROM. The control inputs still manage traditional
read, standby, output disable, and Auto select modes.
Command Register
The command register is enabled only when high volt-
age is applied to the V
gramming operations are only accessed via the
register. In addition, two-cycle commands are required
for erase and reprogramming operations. The tradi-
tional read, standby, output disable, and Auto select
modes are available via the register.
The device’s command register is written using standard
microprocessor write timings. The register controls an
internal state machine that manages all device opera-
tions. For system design simplification, the device is de-
signed to support either WE# or CE# controlled writes.
During a system write cycle, addresses are latched on
the falling edge of WE# or CE# whichever occurs last.
Data is latched on the rising edge of WE# or CE# which-
ever occur first. To simplify the following discussion, the
WE# pin is used as the write cycle control pin throughout
the rest of this text. All setup and hold times are with re-
spect to the WE# signal.
OVERVIEW OF ERASE/PROGRAM
OPERATIONS
Embedded Erase Algorithm
AMD now makes erasure extremely simple and reli-
able. The Embedded Erase algorithm requires the user
to only write an erase setup command and erase com-
mand. The device will automatically pre-program and
verify the entire array. The device automatically times
the erase pulse width, provides the erase verify and
counts the number of sequences. A status bit, Data#
Polling, provides feedback to the user as to the status
of the erase operation.
Embedded Programming Algorithm
AMD now makes programming extremely simple and
reliable. The Embedded Programming algorithm re-
8
PP
voltage, the device functions as a
PP
pin. The erase and repro-
Am28F020A
5%
quires the user to only write a program setup command
and a program command. The device automatically
times the programming pulse width, provides the pro-
gram verify and counts the number of sequences. A
status bit, Data# Polling, provides feedback to the user
as to the status of the programming operation.
DATA PROTECTION
The device is designed to offer protection against acci-
dental erasure or programming caused by spurious
system level signals that may exist during power transi-
tions. The device powers up in its read only state. Also,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences.
The device also incorporates several features to pre-
vent inadver tent write cycles resulting from V
power-up and power-down transitions or system noise.
Low V
To avoid initiation of a write cycle during V
and power-down, the device locks out write cycles for
V
ages). When V
abled, all internal program/erase circuits are disabled,
and the device resets to the read mode. The device ig-
nores all writes until V
that the control pins are in the correct logic state when
V
Write Pulse “Glitch” Protection
Noise pulses of less than 10 ns (typical) on OE#, CE#
or WE# will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE# = V
CE#=V
and WE# must be a logical zero while OE# is a logical
one.
Power-Up Write Inhibit
Power-up of the device with WE# = CE# = V
OE# = V
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
CC
CC
> V
< V
IH
CC
LKO
LKO
IH
or WE# = V
Write Inhibit
will not accept commands on the rising
to prevent unintentional writes.
(see DC characteristics section for volt-
CC
< V
LKO
CC
IH
. To initiate a write cycle CE#
> V
, the command register is dis-
LKO
. The user must ensure
CC
power-up
IL
and
CC
IL
,