AK4122VQ ETC [List of Unclassifed Manufacturers], AK4122VQ Datasheet
AK4122VQ
Related parts for AK4122VQ
AK4122VQ Summary of contents
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ASAHI KASEI The AK4122 is a digital sample rate converter (SRC) with the digital audio receiver (DIR). The input sample rate ranges from 8kHz to 96kHz. The output sample rate is 32kHz, 44.1kHz, 48kHz or 96kHz. By using the AK4122, ...
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ASAHI KASEI Block Diagram RX1 RX1 RX2 RX2 RX3 RX3 RX4 RX4 DIR IPS1-0 PORT1 BICK1 BICK1 Serial LRCK1 LRCK1 Audio SDTI I/F ISEL1-0 SDTI PORT2 BICK2 BICK2 Serial LRCK2 LRCK2 Audio SDTIO I/F SDTIO MCLK2 AVDD AVSS MS0267-E-03 INT0 ...
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... Pin Layout 48 47 CDTI 1 CDTO 2 TST1 3 INT2 4 TST2 5 TST3 6 M/S2 7 M/S3 8 SMUTE 9 TST4 10 TST5 11 FILT 12 13 MS0267-E-03 48pin LQFP (0.5mm pitch AK4122VQ Top View [AK4122 SDTIO 35 BICK2 34 LRCK2 33 MCLK2 32 DVDD 31 DVSS 30 SDTI 29 ...
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ASAHI KASEI No. Pin Name I/O 1 CDTI I Control Data Input Pin 2 CDTO O Control Data Output Pin 3 TST1 O Test 1 Pin 4 INT2 O Interrupt 2 Pin 5 TST2 O Test 2 Pin Test 3 ...
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ASAHI KASEI External Resistor Pin 12kΩ±5% resistor should be connected to AVSS externally. 26 AVSS - Analog Ground Pin Power-Down Mode Pin 27 PDN I “H”: Power up, “L”: Power down reset and initializes the control register. ...
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ASAHI KASEI Handling of Unused pins The unused digital I/O pins should be processed appropriately as below. Classification Pin Name PORT1 BICK1, LRCK1, SDTI MCLK2 BICK2, LRCK2 PORT2 SDTIO M/S2 OMCLK BICK, LRCK PORT3 SDTO M/S3 RX1, RX2, RX3, RX4 ...
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ASAHI KASEI (AVSS, BVSS, DVSS=0V; Note 1) Parameter Power Supplies: Analog Digital |BVSS − DVSS| Input Current, Any Pin Except Supplies Digital Input Voltage 1 (Except RX1-4 pins) Digital Input Voltage 2 (RX1-4 pins) Ambient Temperature (Power applied) Storage Temperature ...
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ASAHI KASEI (Ta=25°C; AVDD=DVDD=3.3V; AVSS=BVSS=DVSS=0V; data = 24bit; measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.) Parameter SRC Characteristics: Resolution Input Sample Rate Output Sample Rate THD+N (Input = 1kHz, 0dBFS, Note 5) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz ...
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ASAHI KASEI (Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; DEM=OFF) Parameter Digital Filter Passband −0.001dB 0.985 ≤ FSO/FSI ≤ 6.000 0.905 ≤ FSO/FSI < 0.985 0.714 ≤ FSO/FSI < 0.905 0.656 ≤ FSO/FSI < 0.714 0.536 ≤ FSO/FSI < 0.656 0.492 ≤ ...
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ASAHI KASEI (Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; C Parameter Master Clock Timing Frequency Pulse Width Low Pulse Width High LRCK for Input data (LRCK1, LRCK2) Frequency Duty Cycle LRCK for Output data (LRCK, LRCK2) Frequency Duty Cycle Slave Mode Master ...
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ASAHI KASEI Parameter Output for PORT3 (Slave mode) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” BICK “↑” to LRCK Edge LRCK to SDTO (MSB) (Except I BICK “↓” to SDTO Output for PORT2 ...
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ASAHI KASEI Timing Diagram MCLK tCLKH LRCK BICK tBCKH LRCK tBLR BICK tLRS SDTO SDTI Note : BICK shows BICK1 of PORT1, BICK2 of PORT2 and BICK of PORT3. LRCK shows LRCK1 of PORT1, LRCK2 of PORT2 and LRCK of ...
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ASAHI KASEI LRCK tMBLR BICK SDTO SDTI Note : BICK shows BICK1 of PORT1, BICK2 of PORT2 and BICK of PORT3. LRCK shows LRCK1 of PORT1, LRCK2 of PORT2 and LRCK of PORT3. SDTI shows SDTI of PORT1 or SDTIO ...
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ASAHI KASEI CSN CCLK CDTI D2 CDTO CSN CCLK CDTI A1 Hi-Z CDTO MS0267-E-03 tCSH D1 D0 Hi-Z WRITE Data Input Timing A0 tDCD D7 READ Data Output Timing [AK4122] tCSW VIH VIL VIH VIL VIH ...
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ASAHI KASEI CSN CCLK CDTI CDTO D2 PDN MS0267-E-03 tCSW tCSH tCCZ D1 D0 READ Data Output Timing 2 tPD Power Down & Reset Timing - 15 - [AK4122] VIH VIL VIH VIL VIH VIL Hi-Z 50%DVDD VIL 2004/08 ...
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ASAHI KASEI Internal Signal Path The input source of the SRC can be switched between the outputs of the DIR, PORT1 or PORT2. The input source of the PORT2 and PORT3 can be switched between the outputs of the SRC ...
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ASAHI KASEI Note 1. In this case, PORT2 is input port. If PORT2 is unused, the digital I/O pins should be processed appropriately by Table 2. M/S2 pin Mode L Slave H Master Note 2. In this case, PORT3 is ...
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ASAHI KASEI Master Mode and Slave Mode When PORT2 and PORT3 are used as output port, the M/S2 pin and M/S3 pin select either master or slave mode. “H” is master mode, “L” is slave mode. In master mode, MCLK ...
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ASAHI KASEI LRCK BICK(64fs) SDTI( 23:MSB, 0:LSB LRCK BICK(64fs SDTI(i) 23:MSB, 0:LSB LRCK BICK(64fs) Don't Care SDTI(i) 23:MSB, 0:LSB (2) PORT2 Four kinds of data formats can ...
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ASAHI KASEI LRCK BICK(32fs SDTIO(o) SDTIO( BICK(64fs) SDTIO( Don't Care SDTIO(i) SDTIO-23:MSB, 0:LSB SDTIO-15:MSB, 0:LSB LRCK BICK(64fs SDTIO(o) ...
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ASAHI KASEI (3) PORT3 Two kinds of data formats can be chosen with the ODIF bit (Table 10). In both modes, the serial data is in MSB first, 2’s compliment format. The SDTO is clocked out on the falling edge ...
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ASAHI KASEI Soft Mute Operation Soft mute operation is performed in the digital domain of the SRC output. Soft mute can be controlled by SMUTE bit or SMUTE pin. The SMUTE bit and SMUTE pin are ORed between pin and ...
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ASAHI KASEI De-emphasis Filter Control The AK4122 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). (1) When input port is DIR When the input port is DIR and DEAU bit ...
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ASAHI KASEI System Reset Bringing the PDN pin = “L” sets the AK4122 power-down mode and initializes the digital filter. When PDN pin = “L”, the SDTO output is “L”. The AK4122 should be reset once by bringing PDN pin ...
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ASAHI KASEI 96kHz Clock Recovery The on-chip, low jitter PLL of DIR has a wide lock range of 32kHz to 96kHz and a lock time of less than 20ms. The AK4122 has a sampling frequency detect function (32kHz, 44.1kHz, 48kHz, ...
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ASAHI KASEI Biphase signal input circuit 75Ω Coax Figure 15. Consumer Input Circuit (Coaxial Input) Note 1: Coax input only : if a coupling level to this input from the next RX input line pattern exceeds 50mV, an incorrect operation ...
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ASAHI KASEI Sampling Frequency and Pre-emphasis Detection The AK4122 has two methods for detecting the sampling frequency. The sampling frequency is detected by comparing the recovered clock to the MCLK2 or OMCLK frequency, and the detected frequency is reported on ...
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ASAHI KASEI Interrupt Handling for DIR There are nine events that cause the INT2-0 pins to go “H”. 1. UNLCK: PLL unlock state detection “1” when the PLL loses lock. The AK4122 loses lock when the distance between two preambles ...
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ASAHI KASEI (1) UNLCK, PAR, AUTO, V and AUDN bits Interrupt (UNLCK, PAR, AUTO, V, AUDN) INT0 pin INT1 pin INT2 pin Register 07H Read 07H BICK, LRCK (UNLCK) BICK, LRCK (except UNLCK) SDTIO / SDTO (AMUTE = “1”) (UNLCK, ...
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ASAHI KASEI (2) STC, CINT and QINT bits Interrupt (FS3-0, PEM, C-bit, Q-sub) Interrupt (STC, CINT, QINT) INT0 pin INT1 pin INT2 pin Register 07H Read 07H BICK, LRCK SDTIO / SDTO Figure 18. INT2-0 Timing (STC, CINT, QINT bits) ...
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ASAHI KASEI (3) DAT bit Interrupt (DAT) INT0 pin INT1 pin INT2 pin Register 08H “0” Read 08H BICK, LRCK SDTIO / SDTO (1) Hold Time : max. 4096/fs (2) Hold Time = 0 MS0267-E-03 (1) (2) Hold “1” “0” ...
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ASAHI KASEI Release Muting Figure 20. Interrupt Handling Sequence Example 1 MS0267-E-03 PD pin ="L" to "H" Initialize Read 07H, 08H INT0/1 pin ="H" No Yes Mute SDTIO / SDTO Read 07H, 08H (Each Error Handling) Read 07H, 08H (Resets ...
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ASAHI KASEI Figure 21. Interrupt Handling Sequence Example 2 MS0267-E-03 PD pin ="L" to "H" Initialize Read 07H No INT1 pin ="H" Yes Read 07H and Detect QSUB= “1” (Read Q-buffer) No New data QCRC = “0” is invalid Yes ...
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ASAHI KASEI Q-subcode buffers The DIR of the AK4122 has a Q-subcode buffer for CD application. The AK4122 takes Q-subcode into registers under the following conditions: 1) The sync word (S0, S1) consists of at least 16 “0”s. 2) The ...
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ASAHI KASEI Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection The DIR of the AK4122 has a Non-PCM steam auto-detection function. When the 32-bit mode Non-PCM preamble based on Dolby “AC-3 Data Stream in IEC60958 Interface” is detected, the NPCM ...
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ASAHI KASEI Register Map Addr Register Name 00H PDN & Mode Control XTL1 01H Selector & Clock Control BYPS 02H Audio Interface Format 03H DIR Control CS12 04H INT0 Mask MULK0 05H INT1 Mask MULK1 06H DAT Mask & DTS ...
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ASAHI KASEI Register Definitions Addr Register Name 00H PDN & Mode Control XTL1 R/W R/W Default PWN: Power Down Control 0 : Power down 1 : Normal operation (Default) “0” powers down all sections. The contents of all register are ...
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ASAHI KASEI Addr Register Name 01H Selector & Clock Control BYPS R/W R/W Default OCKS1-0: OMCLK Frequency Select for Master mode (Table 5) Initial values are “10”. ICKS1-0: MCLK2 Frequency Select for Master mode (Table 4) Initial values are “10”. ...
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ASAHI KASEI Addr Register Name 02H Audio Interface Format R/W Default DIF1-0: Audio Interface Format for PORT1 (Table 8) Initial values are “01”. IDIF1-0: Audio Interface Format for PORT2 (Table 9) Initial values are “01”. ODIF: Audio Interface Format for ...
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ASAHI KASEI Addr Register Name 04H INT0 Mask MULK0 R/W R/W Default MQIT0: Mask enable for QINT bit 0 : Mask disable 1 : Mask enable MCIT0: Mask enable for CINT bit 0 : Mask disable 1 : Mask enable ...
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ASAHI KASEI Addr Register Name 05H INT1 Mask MULK1 R/W R/W Default MQIT1: Mask enable for QINT bit 0 : Mask disable 1 : Mask enable MCIT1: Mask enable for CINT bit 0 : Mask disable 1 : Mask enable ...
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ASAHI KASEI Addr Register Name 06H DAT Mask & DTS Detect R/W Default MDAT0: Mask enable for DAT bit 0 : Mask disable 1 : Mask enable The factor which mask bit is set to “0” affects INT0 and INT2 ...
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ASAHI KASEI Addr Register Name 07H Receiver Status 0 UNLCK R/W Default QINT: Q-subcode Buffer Interrupt change 1 : Changed This bit goes to “1” when Q-subcode stored in register addresses 13H to 1CH is updated. CINT: ...
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ASAHI KASEI Addr Register Name 08H Receiver Status 1 DAT R/W Default FS3-0: Sampling Frequency Detection (Table 17) PEM: Pre-emphasis Detect (Table 18 OFF This bit is made by encoding the channel status bits. NPCM: ...
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ASAHI KASEI Addr Register Name 0AH RX Channel Status Byte 0 CR7 0BH RX Channel Status Byte 1 CR15 0CH RX Channel Status Byte 2 CR23 0DH RX Channel Status Byte 3 CR31 0EH RX Channel Status Byte 4 CR39 ...
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ASAHI KASEI Burst Preambles in Non-PCM Bitstreams preamble Aux Preamble word Length of field Pa 16 bits Pb 16 bits Pc 16 bits Pd 16 bits MS0267-E-03 sub-frame of IEC60958 ...
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ASAHI KASEI Bits of Pc Value Contents 0-4 data type 0 NULL data 1 Dolby AC-3 data 2 reserved 3 PAUSE 4 MPEG-1 Layer1 data 5 MPEG-1 Layer2 or 3 data or MPEG-2 without extension 6 MPEG-2 data with extension ...
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ASAHI KASEI Non-PCM Bitstream Timing (1) When Non-PCM preamble does not arrive within 4096 frames PDN pin Bit stream AUTO bit Pc Register “0” Pd Register “0” (2) When Non-PCM bitstream stops (when MULK0=0) INT0 ...
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ASAHI KASEI Figure 29 shows the typical system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. • PORT2, PORT3 : Slave Mode uP & DSP ...
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ASAHI KASEI 1. Grounding and Power Supply Decoupling The AK4122 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS, BVSS and DVSS of the ...
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ASAHI KASEI 3. Jitter Tolerance Figure 32 shows the jitter tolerance to ILRCK for AK4122. The jitter frequency and the jitter amplitude shown in Figure 32 define the jitter quantity. When the jitter amplitude is 0.01Uipp or less, the AK4122 ...
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ASAHI KASEI 48pin LQFP(Unit: mm) 9.0 ± 0.2 7 0.22 ± 0.08 0.5 0.10 Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0267-E-03 PACKAGE 25 1.40 ± 0. ...
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... ASAHI KASEI 1 MS0267-E-03 MARKING AKM AK4122VQ XXXXXXX XXXXXXXX: Date code identifier - 53 - [AK4122] 2004/08 ...
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ASAHI KASEI Date (YY/MM/DD) Revision Reason 03/10/03 00 First Edition 04/01/27 01 Spec Change 04/07/23 02 Add Spec Add Spec 04/8/16 03 Add Spec • These products and their specifications are subject to change without notice. Before considering any use ...