AK4122VQ ETC [List of Unclassifed Manufacturers], AK4122VQ Datasheet - Page 24

• Manufacturer Part Number: AK4122VQ
• Description: 24 BIT 96KHZ SRC WITH DIR
• Manufacturer: ETC [List of Unclassifed Manufacturers]

ASAHI KASEI
Bringing the PDN pin = “L” sets the AK4122 power-down mode and initializes the digital filter. When PDN pin = “L”,
the SDTO output is “L”. The AK4122 should be reset once by bringing PDN pin = “L” upon power-up. The SDTO is
valid from less than 100ms after the rising of PDN after clocks are supplied, and until then, outputs “L”. After the rising
of PDN pin, the SDTIO pin is input pin.
The recommended sequence of changing clocks is shown as Figure 14. The internal reset is executed when the input or
the output clocks are changed. The SDTO is placed “0” during reset. Within 100ms, the SDTO outputs normal data.
When the frequency transition occurs gradually without the phase change, the output data may have large distortion for
several seconds. Then, to output normal data within 100ms, a reset by PDN pin = “L” or PWN bit = “0” is recommended
when clocks are changed.
MS0267-E-03
System Reset
Sequence of changing clocks
Note 1. The data on SDTO may cause click noise. If SDTI or SDTIO is “0” from GD before PDN pin goes “L”,
Note 2. SMUTE can remove the unknown data.
External clocks
(internal state)
SDTO
PDN
(input / output port)
External clocks
(input port
PDN pin or
PWN bit
SDTIO / SDTO
SMUTE (Note2,
Att.Level
(internal state)
or output port)
recommended)
the data on SDTO keeps “0” then no unknown data is output.
-
0dB
∞
dB
state 1 (44.1kHz)
normal operation
normal data
Power-down
don’t care
1024/fso
Figure 14. Sequence of changing clocks
Power down
(unknown)
PLL locktime & fs detection
Note1
Figure 13. System Reset
< 100msec
“0” data
PLL locktime
& fs detection
< 100msec
state 2 (48kHz)
- 24 -
(stable)
1024/fso
normal operation
normal operation
normal data
normal data
Power-down
don’t care
“0” data
[AK4122]
2004/08