AK4122VQ ETC [List of Unclassifed Manufacturers], AK4122VQ Datasheet - Page 17

• Manufacturer Part Number: AK4122VQ
• Description: 24 BIT 96KHZ SRC WITH DIR
• Manufacturer: ETC [List of Unclassifed Manufacturers]

ASAHI KASEI
Note 1. In this case, PORT2 is input port. If PORT2 is unused, the digital I/O pins should be processed appropriately
Note 2. In this case, PORT3 is output port. If PORT3 is unused, the digital I/O pins should be processed appropriately
MS0267-E-03
PORT1 can be operated in slave mode only. PORT2 and PORT3 work in master mode and slave mode. Internal system
clock is created by internal PLL using LRCK1, LRCK2 or LRCK of DIR. The MCLK is not needed when PORT2 and
PORT3 are in slave mode and then please set MCLK2 pin and OMCLK pin to DVSS. However, when PORT2 and
PORT3 are used in master mode, MCLK2 pin and OMCLK pin should be supplied to MCLK. The M/S2 pin and M/S3
pin select between master and slave mode. Table 4 and 5 show setting of MCLK frequency that PORT2 and PORT3 are
master mode. In case of detecting the sampling frequency by MCLK when DIR is used, MCLK (MCLK2 or OMCLK) of
selected output port (PORT2 or PORT3) should be input.
System Clock
by Table 2.
by Table 3.
M/S2 pin
M/S3 pin
H
H
L
L
OCKS1
ICKS1
0
0
1
1
0
0
1
1
Master
Master
Mode
Mode
Slave
Slave
OCKS0
ICKS0
Table 5. OMCLK frequency select for Master mode
Table 4. MCLK2 frequency select for Master mode
0
1
0
1
0
1
0
1
Unused pin
Unused pin
OMCLK
OMCLK
MCLK2
MCLK2
LRCK2
LRCK2
BICK2
SDTIO
BICK2
SDTIO
LRCK
SDTO
LRCK
SDTO
BICK
BICK
32kHz ≤ fs ≤ 48kHz
32kHz ≤ fs ≤ 48kHz
Table 2. Pin Setting for PORT2
Table 3. Pin Setting for PORT3
256fs
384fs
512fs
768fs
256fs
384fs
512fs
768fs
Pin I/O
Pin I/O
- 17 -
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
OMCLK
MCLK2
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be open.
This pin should be open.
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be connected to DVSS.
This pin should be open.
This pin should be connected to DVSS.
This pin should be open.
This pin should be open.
This pin should be open.
48kHz < fs ≤ 96kHz
48kHz < fs ≤ 96kHz
256fs
384fs
256fs
384fs
N/A
N/A
N/A
N/A
Setting
Setting
Default
Default
[AK4122]
2004/08