K4D26323QG SAMSUNG [Samsung semiconductor], K4D26323QG Datasheet - Page 14

• Manufacturer Part Number: K4D26323QG
• Description: 128Mbit GDDR SDRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4D26323QG-GC
tQH Timing (CL4, BL2)
Note 1 :
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
- tQHmin = tHP-X where
Power Down Timing
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
COMMAND
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
variation and replaces tDV
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
strobe and all data associated with that data strobe are coincidentally valid.
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
CK, CK
Command
DQS
CK, CK
DQ
CS
CKE
READA
0
VALID
Enter Power Down mode
(Read or Write operation
must not be in progress)
t
1
1
IS
NOP
NOP
2
NOP
- 14 -
Exit Powr Down mode
t
IS
NOP
3
NOP
tDQSQ(max)
3t
CK
4
Qa0
tQH
tHP
128M GDDR SDRAM
NOP
tDQSQ(max)
Qa1
VALID
Rev 1.2(Mar. 2005)
5