K4D26323QG SAMSUNG [Samsung semiconductor], K4D26323QG Datasheet - Page 7

• Manufacturer Part Number: K4D26323QG
• Description: 128Mbit GDDR SDRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4D26323QG-GC
FUNCTIONAL DESCRIPTION
• Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
* When the operating frequency is changed, DLL reset should be required again.
Command
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
*1
*
Power up & Initialization Sequence
1,2
CK,CK
stable for 200us
7. Issue precharge command for all banks of the device.
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL. Minimum 20 clcok cycles are required prior to MRS
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
Inputs must be
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
ALL Banks
precharge
t
RP
EMRS
20 Clock
min.
DLL Reset
MRS
4 Clock min.
ALL Banks
precharge
- 7 -
tRP
1st Auto
Refresh
200 Clock min.
t
RFC
2nd Auto
Refresh
128M GDDR SDRAM
t
RFC
Rev 1.2(Mar. 2005)
command.
Register Set
Mode
4 Clock min.
Command
Any