K4D26323QG SAMSUNG [Samsung semiconductor], K4D26323QG Datasheet - Page 15

• Manufacturer Part Number: K4D26323QG
• Description: 128Mbit GDDR SDRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4D26323QG-GC
AC CHARACTERISTICS (II)
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
Last data in to Row precharge @Normal
Precharge
Last data in to Row precharge @Auto Pre-
charge
Auto precharge write recovery + Precharge tDAL
Row active to Row active
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Exit self refresh to read command
Power down exit time
Refresh interval time
2. The number of clock of tRP is restricted by the number of clock of tRAS and tRP
3. The number of clock of tWR_A is fixed. It can’t be changed by tCK. tWR_A is related with CL. It is equal to CL+1tCK.
4. tRCDWR is equal to tRCDRD-2tCK and the number of clock can not be lower than 2tCK.
5. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer unconditionally.
Parameter
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tWR
tWR_A
tRRD
tCDLR
tCCD
tMRD
tXSR
tPDEX
tREF
Symbol
3tCK+
28.6
Min
200
7.8
45
50
15
10
15
15
tIS
30
6
4
2
1
4
-25
- 15 -
100K
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3tCK+
45.8
51.5
28.6
16.5
16.5
16.5
11.4
Min
200
7.8
tIS
33
6
4
2
1
3
-2A
100K
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
128M GDDR SDRAM
3tCK+
49.5
56.1
16.5
16.5
11.4
16.5
Min
200
7.8
tIS
33
33
5
3
2
1
3
-33
Rev 1.2(Mar. 2005)
100K
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
Note
2,5
4,5
1,5
1,3
3,5
5
5
5
5
1