T5761 ATMEL [ATMEL Corporation], T5761 Datasheet - Page 13

• Manufacturer Part Number: T5761
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 18 illustrates how to set the receiver back to poll-
ing
POLLING/_ON must be held to low for the time period
t
the delay t
time T
This command is faster than using Pin DATA at the cost
of an additional connection to the C.
Figure 19 illustrates how to set the receiver to receiving
mode via the Pin POLLING/_ON. The Pin POLL-
ING/_ON must be held to Low. After the delay t
receiver changes from sleep mode to start–up mode re-
gardless the programmed values for T
As long as POLLING/_ON is held to Low, the values for
T
also chapter ’Digital Noise Suppression’).
If the receiver is polled exclusively by a C, T
be programmed to 31 (permanent sleep mode). In this
case the receiver remains in sleep mode as long as POLL-
ING/_ON is held to High.
Data Clock
The Pin DATA_CLK makes a data shift clock available
to sample the data stream into a shift register. Using this
data clock, a C can easily synchronize the data stream.
This clock can only be used for Manchester and Bi-
phase coded signals.
Generation of the data clock:
After a successful bit check, the receiver switches from
polling mode to receiving mode and the data stream is
available at Pin DATA. In receiving mode, the data clock
control logic (Manchester/Bi-phase demodulator) is ac-
tive and examines the incoming data stream. This is done,
like in the bit check, by subsequent time frame checks
where the distance between two edges is continuously
Rev. A2, 19-Oct-00
on2
Sleep
. After the positive edge on Pin POLLING/_ON and
IC_ACTIVE
POLLING/_ON
Data_out (DATA)
Serial bi–directional
data line
mode
and N
Sleep
on3
elapses.
Bit–check
, the polling mode is active and the sleep
via
Pin
will be ignored, but not deleted (see
POLLING/_ON.
Figure 19. Activating the receiving mode via Pin POLLING/_ON
Sleep mode
Preliminary Information
Sleep
and N
The
Sleep
Bit–check
on1
t
on1
must
, the
Pin
.
Start–up mode
compared to a programmable time window. As illustrated
in figure 20, only two distances between two edges in
Manchester and Bi-phase coded signals are valid (T and
2T).
The limits for T are the same as used for the bit check.
They can be programmed in the LIMIT-register
(Lim_min and Lim_max, see tables 10 and 11).
The limits for 2T are calculated as follows:
Lower limit of 2T:
Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min) / 2
Upper limit of 2T:
Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min) / 2
(If the result for ’Lim_min_2T’ or ’Lim_max_2T’ is not
an integer value, it will be round up)
The data clock is available, after the data clock control
logic has detected the distance 2T (Start bit) and is issued
with the delay t
ure 20).
If the data clock control logic detects a timing or logical
error (Manchester code violation), like illustrated in fig-
ures 21 and 22, it stops the output of the data clock. The
receiver remains in receiving mode and starts with the bit
check. If the bit check was successful and the start bit has
been detected, the data clock control logic starts again
with the generation of the data clock (see figure 23).
It is recommended to use the function of the data clock
only in conjunction with the bit check 3, 6 or 9. If the bit
check is set to 0 or the receiver is set to receiving mode
via the Pin POLLING/_ON, the data clock is available if
the data clock control logic has detected the distance 2T
(Start bit).
Note that for Bi-phase-coded signals, the data clock is is-
sued at the end of the bit.
Delay
T5760 /
after the edge on Pin DATA (see fig-
Receiving mode
X
X
T5761
13 (32)