T5761 ATMEL [ATMEL Corporation], T5761 Datasheet - Page 6

• Manufacturer Part Number: T5761
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

Polling Circuit and Control Logic
The receiver is designed to consume less than 1 mA while
being sensitive to signals from a corresponding trans-
mitter. This is achieved via the polling circuit. This circuit
enables the signal path periodically for a short time.
During this time the bit-check logic verifies the presence
of a valid transmitter signal. Only if a valid signal is
detected the receiver remains active and transfers the data
to the connected C. If there is no valid signal present the
receiver is in sleep mode most of the time resulting in low
current consumption. This condition is called polling
mode. A connected C is disabled during that time.
All relevant parameters of the polling logic can be config-
ured by the connected C. This flexibility enables the
user to meet the specifications in terms of current con-
sumption, system response time, data rate etc.
Regarding the number of connection wires to the mC, the
receiver is very flexible. It can be either operated by a
T5760 T5761
6 (32)
Figure 6. Narrow band receiving frequency response
Figure 7. Wide band receiving frequency response
–100
–10
–20
–30
–40
–50
–60
–20
–40
–60
–80
0
0
–12
–4
–3
–9
/
–2
–6
–1
–3
df ( MHz )
df ( MHz )
0
0
1
3
Preliminary Information
2
6
3
9
12
4
single bi-directional line to save ports to the connected mC
or it can be operated by up to five uni-directional ports.
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the
analog filtering is derived from one clock. This clock
cycle T
combination with a divide by 14 circuit. According to
chapter ‘RF Front End’, the frequency of the crystal oscil-
lator (f
also defines the operating frequency of the local oscillator
(f
T
T
T
ters:
D Timing of the polling circuit including bit check
D Timing of the analog and digital signal processing
D Timing of the register programming
D Frequency of the reset marker
D IF filter center frequency (f
Most applications are dominated by two transmission fre-
quencies: f
f
usage of all T
characteristics display three conditions for each parame-
ter.
D Application USA
D Application Europe
D Other applications
The clock cycle of some function blocks depends on the
selected baud-rate range (BR_Range) which is defined in
the OPMODE register. This clock cycle T
by the following formulas for further reference:
BR_Range = BR_Range0: T
Polling Mode
According to figure 11, the receiver stays in polling mode
in a continuous cycle of three different modes. In sleep
mode the signal processing circuitry is disabled for the
time period T
I
processing circuits are enabled and settled. In the follow-
Transmit
S
Clk
Clk
Clk
LO
= I
(f
(f
The electrical characteristic is given as a function of
T
). The basic clock cycle is T
controls the following application-relevant parame-
= 2.066 ms
= 1.961 ms for f
Clk
XTO
XTO
Soff
XTO
Clk
.
. During the start-up period, T
= 868.3 MHz in Europe. In order to ease the
= 7.14063 MHz, T
= 6.77617 MHz, T
) is defined by the RF input signal (f
is derived from the crystal oscillator (XTO) in
Transmit
Clk
BR_Range1: T
BR_Range2: T
BR_Range3: T
Sleep
-dependent parameters on this electrical
= 915 MHz is mainly used in USA,
RF
while consuming low current of
for
= 915 MHz
Clk
Clk
XClk
XClk
XClk
XClk
f
RF
IF0
= 1.961 s)
= 2.066 s)
= 868.3 MHz
)
= 8
= 4
= 2
= 1
Clk
Rev. A2, 19-Oct-00
= 14/ f
Startup
T
T
T
T
XClk
Clk
Clk
Clk
Clk
XTO
RFin
, all signal
is defined
) which
giving
and