LC89052TA-E SANYO [Sanyo Semicon Device], LC89052TA-E Datasheet - Page 13

• Manufacturer Part Number: LC89052TA-E
• Description: Digital Audio Interface Receiver
• Manufacturer: SANYO [Sanyo Semicon Device]

8.3.3 Output clocks (CKOUT, BCK, LRCK)
• The clock source for the clocks output from CKOUT, BCK, and LRCK can be selected from two master clocks, the
• Normally, when the PLL circuit is locked, the master clock is switched to the PLL source, and when the PLL circuit is
• Clock switching depends on the PLL circuit locked/unlocked state at the time of the register setup. If the PLL source
• When VCO operation is stopped with PLLOPR, XIN becomes the clock source. However, clock continuity cannot be
• Either the PLL clock or the XIN clock is output from the CKOUT pin. The divided clock of CKOUT is output from
• The PLL lock time frequency is set with PLLCK[1:0]. However, it is possible to maintain clock continuity without
• If you use the following procedure to switch between 512fs and (512/2)fs, the BCK and LRCK output clock
PLL circuit and the XIN pin.
unlocked, the master clock automatically switches to the XIN source. To switch the clock source forcibly, set with
OCKSEL. Clock continuity is maintained when the clock source is selected by the locked/unlocked state of the PLL
circuit or OCKSEL.
is selected with OCKSEL when the PLL circuit is unlocked, the clock is automatically switched after the PLL circuit
is locked.
maintained if the operation is stopped with PLLOPR while the PLL circuit is locked. When a low-power mode is set,
continuity cannot be maintained if the mode is switched from the locked PLL.
the BCK pin and LRCK pin.
losing the PLL locked state when switching, in the PLL locked state, from the 512fs setting mode with PLLCK[1:0] =
"10" to the (512/2)fs setting with the PLLCK[1:0] = "11", as well as when switching in the reverse direction.
continuity can be maintained, and the CKOUT output clock frequency can be held within a narrow band. Other
PLLCK[1:0] switching would result in a lock error.
Clock source
PLL state
OCKSEL
Figure 8.4 Flowchart for CKOUT Output Clock Narrow Band Operation
Table 8.4 Register Settings, PLL States, and the Clock Source
Locked
PLL
No
CKOUT output
24.576MHz
calculation
Data input
512fs set
detection
LOCK
fs
fs=48kHz
0
Yes
LC89052TA-E
fs=96kHz
PLLCK0=0
PLLCK1=1
Unlocked
XIN
(512/2)fs set
PLLCK0=1
PLLCK1=1
Locked
XIN
1
Unlocked
XIN
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