LC89052TA-E SANYO [Sanyo Semicon Device], LC89052TA-E Datasheet - Page 26

• Manufacturer Part Number: LC89052TA-E
• Description: Digital Audio Interface Receiver
• Manufacturer: SANYO [Sanyo Semicon Device]

8.7.3 Output of clock switch transition signal
• This section describes the operation when
• A clock switching transitional period signal is a signal that reports a clock switching condition to external circuits due
• After setting GPISEL, high level is output from
• In the lock in process, the
• In the unlock process, the
period.
to a change in the PLL locked/unlocked state. This signal allows the application to grasp the PLL lock state
transitions and the timing of change in the clock signals. This setup is selected with GPISEL.
change in the PLL circuit locked/unlocked state.
detected and PLL is locked. After a certain period, it rises with the same timing as ERROR.
and it rises after the word clocks generated from the XIN clock are counted for a certain period.
PLL lock state
PLL lock state
XTAL clock
XTAL clock
VCO clock
VCO clock
ERROR
ERROR
CKOUT
CKOUT
UGPI
UGPI
RXIN
RXIN
__________
__________
UGPI low pulse falls at the same timing as ERROR, which is the PLL lock detecting signal
Digital data
UGPI low pulse rises with the word clock generated by the XIN clock after input data is
Locked
Unlocked
Figure 8.14 Clock Switching Timing
__________
UGPI is selected as an output pin during the clock switching transitional
(a) : During the lock-in process
(b) : During the unlock process
__________
UGPI . Low pulse is output when the output clock changes due to the
LC89052TA-E
Digital data
After PLL lock
With the same timing as ERROR
15 ms to 50 ms
Locked
Unlocked
With the same timing
as ERROR
64/fs (s)
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