LC89052TA-E SANYO [Sanyo Semicon Device], LC89052TA-E Datasheet - Page 33

• Manufacturer Part Number: LC89052TA-E
• Description: Digital Audio Interface Receiver
• Manufacturer: SANYO [Sanyo Semicon Device]

FSSEL3
DI15
DI7
0
GPISEL:
GPIDAT:
FLIMIT:
FS4XIN:
FSSEL[3:0]:
RDTMUT
FSSEL2
DI14
DI6
Table 9.6 Input Register Function Settings 1: I/O Data Settings (0xE9)
__________
0: Outputs the microcontroller interface register state. (initial value)
1: Outputs clock switching transitional period signal.
__________
0: Outputs the low level.
1: Outputs the high level. (initial value)
Input data reception limit setting
0: Reception is not limited. All data within the PLL locked range can be received.
1: Reception is limited. The input fs calculation result is reflected in the error flag
Input fs calculation range setting
0: Perform fs calculation for input data in the range of 32k to 96 kHz. (initial value)
1: Perform fs calculation for input data in the range of 64k to 192 kHz.
Input data reception range setting (When FLIMIT = "1" and FS4XIN = "0")
0000: 32k, 44.1k, 48k, 64k, 88.2k, or 96kHz (initial value)
0001: 32kHz only
0010: 44.1kHz only
0011: 48kHz
0100: 88.2kHz only
0101: 96kHz only
0110: 44.1k or 88.2kHz only
0111: 48k or 96kHz only
1000: 32k or 44.1k or 48kHz
1001-1111:Reserved
UGPI pin setting
UGPI output setting (valid only when register output mode is set.)
(initial value)
according to the FSSEL[3:0] setting.
RDTSTA
FSSEL1
DI13
DI5
RDTSEL
FSSEL0
DI12
DI4
LC89052TA-E
FS4XIN
DI11
DI3
0
OFSEL2
FLIMIT
DI10
DI2
OFSEL1
GPIDAT
DI1
DI9
No.7457-33/42
OFSEL1
GPISEL
DI0
DI8