LC89057W-VF4A-E SANYO [Sanyo Semicon Device], LC89057W-VF4A-E Datasheet
LC89057W-VF4A-E
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LC89057W-VF4A-E Summary of contents
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... LC89057W-VF4A-E 1. Overview The LC89057W-VF4A audio IC that demodulates and modulates signals according to data transfer format between digital audio devices via the IEC60958/61937 and EIAJ CP-1201 and supports up to 192kHz of sampling frequency. It features a built-in VCO and oscillation amplifier, two bit clock circuits that are capable of setting independently the frequency-dividing ratios that can also be used for the DSP data input/output clocks, and LR clock output pins ...
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... A continuous switching operation between external clock synchronous mode and PLL clock synchronous mode is possible. • Single 3.3V-power supply operation. TTL input port supports 5V interface. • Adopts small SQFP48 package for efficient use of substrate mounting area. Package Dimensions unit : mm (typ) 3163B 9.0 7 0.5 0.18 (0.75) SANYO : SQFP48(7X7) LC89057W-VF4A-E 0.15 No.7202-2/59 ...
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... Output pin of serial audio data 22 SBCK O S system bit clock output pin (32fs, 64fs, 128fs) 23 SLRCK O S system LR clock output pin (fs/2, fs, 2fs) 24 SDIN I Input pin of serial audio data 5 LC89057W-VF4A LC89057W-VF4A Top view 24 SDIN 23 SLRCK ...
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... Pin demodulation function master or an input pin for slave setting, when pin 41 = "L". 4) Pin modulation function or an input pin for general-purpose I/O function switch setting, when pin 41 = "L". 5) ON/OFF for all power supplies must be done at the same timing as a latch-up countermeasure. LC89057W-VF4A-E Function = -0 ...
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... DIR function: Setting of RERR wait time after PLL is locked DIR function: Setting of clock wait time after PLL is unlocked DIR function: Channel status bit output DIR function: Preamble B info output DIT function: System clock DIT function: Preamble B info output LC89057W-VF4A-E EMPHA/UO/CO AUDIO/VO INT 32 33 Cbit, Ubit Demodulation Input & ...
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... Supply voltage Input voltage range Input voltage range Operating temperature Topr 8-2-1: RX1, RBCK, RLRCK, XIN, TMCK/PIO0, TBCK/PIO1, TLRCK/PIO2, TDATA/PIO3, TXO/PIOEN pins 8-2-2: RX0, RX2, RX3, RX4, RX5/VI, RX6/UI, SDIN, DI, CE, CL, XMODE pins LC89057W-VF4A-E Symbol Conditions 8-1-1 8-1-2 8-1-3 8-1-4 8-1-5 8-1-6 _____ ...
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... Before capacitance of RX1 input pin 8-3-8: Demodulation function and oscillation amplifier stopped, modulation only, output sampling frequency = 96kHz 8-3-9: XIN input continuous 24.576MHz oscillation, demodulation only, input sampling frequency = 96kHz 8-3-10: XIN input continuous 24.576MHz oscillation, modulation, input/output sampling frequency = 96kHz LC89057W-VF4A-E Symbol Conditions 8-3-1 ...
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... TCKSEL = 0 setting (256fs), the falling edge of TBCK is in synchronization with the rising edge of TMCK. TCKSEL = 1 setting (128fs), the falling edge of TBCK is in synchronization with the falling edge of TMCK. RMCK (O) RBCK (O) RDATA (O) RLRCK (O) RX* (I) TMCK (I) TBCK (I) TDATA (I) TLRCK (I) LC89057W-VF4A-E Conditions 8-4-1 8-4-2 8-4-3 8-4-4 8-4-5 t RDI t WMI t WBI t WBI ...
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... CL, CE hold time t CL hold CL, DO delay time CE, DO delay time 8-5-1: When INTOPF is set to "1" input sampling frequency t INTdw INT Figure 8.2 Microcontroller Interface AC Characteristics LC89057W-VF4A-E Conditions 8-5-1 t CLdw t CLuw t CEhold t DIhold t DIsetup t CLtoDO t CEtoDO Hi-Z Ratings min typ ...
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... Modulation function or general-purpose I/O function 3. XMODE Set pin state Undefined Figure 9.1 Setting Timing Chart of Function Setting Input Pins LC89057W-VF4A-E ______ INT are not pulled up or down, their pin state is unstable at the time Table 9.1: Pin Names and Settings Setting Normal system operation range Setting completed 3 ...
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... The chip address setting is required even when only one LC89057W-VF4A-E is used in the system. If the chip address is not set, the chip address is undefined and the microcontroller cannot control the system. When the microcontroller is not used, a chip address-setting pin is input open while XMODE is "L". Be sure to connect either a pull-down resistor or a pull-up resistor to EMPHA/UO/CO and Table 9 ...
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... For this setting, connects either a 10kΩ pull-down or a pull-up resistor to • Set to the master mode normally, when single LC89057W-VF4A used. When multiple LC89057W-VF4A-E ICs are used, set one of them to the master mode and the others to the slave mode. ...
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... In normal demodulation processing, the built-in PLL generates a clock that is synchronized with data and carries out data processing with the clock. In the LC89057W-VF4A-E, data processing can be also done by providing a clock synchronized with data instead of the PLL-generated clock via an independent transmission path. ...
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... Oscillation amplifiers (XIN, XOUT, XMCK) • The LC89057W-VF4A-E features a built-in oscillation amplifier. Connecting a quartz resonator, feedback resistor, and load capacitance to XIN and XOUT can configure an oscillation circuit. When connecting a quartz resonator, use one with a fundamental wave. Be aware that the load capacitance depends on the quartz resonator characteristics. ...
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... When the PLL changes from the locked status to the unlocked, the timing for switching the clock from the PLL source to the XIN source can be changed with XTWT [1:0]. Use these commands if noise occurs during clock switching. LC89057W-VF4A-E R System Output Clock S System Output Clock ...
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... The contents in the square brackets [∗∗∗] by the switch and function blocks correspond to the write command names. • Lock/Unlock is automatically switched by PLL locking/unlocking. [PLLOPR] [PLLSEL] Selected Biphase PLL (256fs or 512fs) TMCK (I) 256fs or 512fs [AMPOPR0] [AMPOPR1] XIN (I) XOUT (O) LC89057W-VF4A-E [PRSEL0] [PRSEL1] [EXSYNC] 1/N (N= [XRSEL0] [XINSEL] [XRSEL1] 1/N 1/N (N=1, 2) (N= ...
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... Output clocks (RMCK, RBCK, RLRCK, SBCK, SLRCK) • The LC89057W-VF4A-E features two clock systems (R and S systems) in order to supply the various needed clocks to peripheral devices such as A/D converter and DSP. • The clock output settings for the R and S systems are done with PRSEL[1:0], XRSEL[1:0], XRBCK[1:0], XRLRCK[1:0], PSBCK[1:0], PSLRCK[1:0], XSBCK[1:0], and XSLRCK[1:0]. • ...
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... Master/Slave is switched by master/slave function switching of demodulation function. Master Clock Generator XTAL Source 12.288MHz or 24.576MHz PLL Source 256fs or 512fs TMCK Source 256fs or 512fs LC89057W-VF4A-E Lock / Unlock [PRSEL] 512fs / 256fs 256fs / 128fs 128fs / 64fs MUTE 12.288MHz / 24.576MHz [XRSEL] 6.144MHz / 12.288MHz 3.072MHz / 6.144MHz ...
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... XTAL clock VCO clock CKST RERR RMCK RX0 to RX6 Digital data PLL status XTAL clock VCO clock CKST RERR RMCK LC89057W-VF4A-E ____________ CKST ) Digital data UNLOCK LOCK After PLL lock 45ms to 300ms Same timing as RERR (a): Lock-in stage UNLOCK UNLOCK Same timing as RERR (b): Unlock stage Figure 10 ...
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... The interval from pin switching through RISEL [2:0] until the data is received is about 250μs to 350μs. In this function, the oscillation amplifier also needs to be set to the continuous operation mode. Input pin selection Internal supply signal Figure 10.5 Input Pin Selecting Process via PLL Unlock LC89057W-VF4A-E Input Data Reception Range 28kHz to 105kHz 28kHz to 195kHz RX0 ...
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... When RX1 is selected and the input signal to RX1 is always fixed to either "H" or "L", RX0 and RX2 processes are not required. In this case, all 7 input pins can be used validly. Coaxial Optical LC89057W-VF4A-E LC89057W-VF4A-E 0.1μF 75Ω Optical etc. (a):Coaxial input circuit LC89057W-VF4A-E 100Ω Optical etc. (b):Optical input circuit Figure 10.6 Bi-Phase Signal Input Circuits RX0 RX1 RX2 RX3 RX4 ...
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... Right-adjusted output is valid only in the master mode. In the slave mode, data is not output correctly. • Output data is output synchronized with the RLRCK edge immediately after the RERR output becomes "L". RLRCK (O) RBCK (O) RDATA (O) RLRCK (O) RBCK (O) RDATA (O) RLRCK (O) RBCK (O) LSB RDATA (O) LC89057W-VF4A L-ch MSB LSB MSB max. 24bit 2 (0 data output L-ch MSB ...
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... The format of the serial audio data input to SDIN and the demodulation data output format must be identical. The initial value of modulation data output is I SDIN (I) RLRCK (O) RBCK (O) RDATA (O) SDIN (I) RLRCK (O) RBCK (O) RDATA (O) SDIN (I) LSB RLRCK (O) RBCK (O) LSB RDATA (O) LC89057W-VF4A max. 24bit MSB LSB MSB L-ch MSB LSB MSB 2 (0 data input max. 24bit MSB ...
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... PLL status. PLL status UNLOCK CKST RERR RDATA SDIN data PLL status LOCK CKST RERR RDATA Demodulation data Figure 10.9 Timing Chart of RDATA Output Data Switching LC89057W-VF4A-E LOCK Muted (a): Lock-in stage UNLOCK Muted (b): Unlock stage Demodulation data SDIN data No.7202-24/59 ...
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... Registers DO4 through DO7 hold the encoded result, while DO8 through DO15 hold the calculated counter value. However, as the calculation count value is output in 8 bit units, fs capable of being calculated are greater than 24kHz. For details, see Chapter 12. Microcontroller Interface. LC89057W-VF4A-E SDIN [RDTSEL] ...
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... If a setting which regard non-PCM data input as an error is made with RESEL, RERR turns to “H” when non-PCM data input is detected. At this time, the PLL locked status and various output clocks are subject to the input data, but the output data is muted. LC89057W-VF4A-E No.7202-26/59 ...
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... Figure 10.11 shows an example of data processing upon occurrence of a parity error. 1occurrence Input data L-1 R-1 L-2 RERR RLRCK RDATA L-0 R-0 Figure 10.11 Example of Data Processing upon Parity Error Occurrence LC89057W-VF4A-E Input Parity Error (a) “L” “L” “L” Output “L” “L” “L” “L” “L” “L” ...
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... EMPHA outputs shows whether there are 50/15μs emphasis parameters for consumer and broadcast studio. EMPHA is immediately output upon detection of RERR even during "H" output. EMPHA L H LC89057W-VF4A-E 45ms to 300ms OK Output start from RLRCK edge immediately after RERR flag is lowered ________ ...
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... The UOSSEL setting, however, is enabled only when PESEL1 is set disabled if PBSEL1 is set to 1. The state of PBSEL0 has nothing to do with this processing • The user data transferred in units of each sub-frame are output in the following timing. RLRCK RBCK UO LC89057W-VF4A-E ____________ AUDIO/VO by switching the contents of Table 10.8 VO Output Output Conditions No error (not burst data) Error (May be burst data) Figure 10 ...
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... B with DIR function and DIT function from PB at once because they share the terminal. • In case of setting preamble B synchronization signal output with DIR function, the channel status data is output from EMPHA/UO/CO pin, and the setting of UOSEL is invalid. LC89057W-VF4A-E c0 Lch c0 Rch c1 Lch c1 Rch ...
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... PaPb detection during 4096 frames YES IEC61937 flag OK INT lowered PaPb detection during 4096 frames YES IEC61937 data hold Figure 10.16 IEC61937 and DTS-CD/LD Data Detection Sequence LC89057W-VF4A Frame counter reset NO IEC61937 flag not valid INT lowered * NO * Depending on the frame count, · ...
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... For the channel status, the first 48 bits of data can be written with the microcontroller interface. • TXO is fixed to "L" by setting TXOPR to stop or TXMUT. TLRCK (I) TBCK (I) TDATA (I) TLRCK (I) TBCK (I) TDATA (I) LC89057W-VF4A-E ______ INT with a 10kΩ resistor. For further information about the 2 S. Switching to MSB-first right-adjusted input is set with TXDFS. L-ch MSB LSB MSB max ...
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... It is also possible to write user data using the preamble B sync signal as the reference. Generation of the preamble B sync signal is configured in PBSEL[1: the case of the DIR function. After the setting, the signal is output from CKST/PB. TLRCK TBCK UI Internal latch signal LC89057W-VF4A-E Table 11.1 RX5/V1 Input Output Conditions No error Error L1 R1 ...
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... Channel status write is synchronized with the output rate. • The validity flag and user data are written in units of frame. Input the same data to the L and R channels. • To process the stereo signals of two channels with this setting, two units of LC89057W-VF4A-E are required. TLRCK R0 L1 ...
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... CS data input Write Interrupt data output Read fs data output Read CS data output Read Pc data output Read LC89057W-VF4A-E _____ INT , CL, CE, DI, DO) ______ INT outputs OR calculation result of the selected Table 12.1 Interrupt Source Setting Contents Description ______ AUDIO pin status has changed ______ INT output following the occurrence of an interrupt source is set to the " ...
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... CE. • outputs are shared using multiple LC89057W-VF4A-E units possible to set the DO outputs of the LC89057W-VF4A-E units of which data is not to be read to be always in the high impedance state with DOEN. With this setting, only the targeted outputs can be read. 12.1.5 I/O timing ...
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... TEST • The shaded parts of DI8 to DI15 in the command area are reserved bits. Input must be doing "0". • Command addresses 0x12 to 0x15 are reserved for testing purposes. Writing to these addresses is prohibited. LC89057W-VF4A-E Table 12.3 Write Register Map DI14 DI13 DI12 0 TXOPR ...
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... TESTM Test mode setting 0: Normal operation (initial value) 1: Enter test mode • When reset by SYSRST is done or the demodulation is set to stop with RXOPR, RBCK and SBCK output "L", and RLRCK and SLRCK output "H". LC89057W-VF4A-E DI5 DI4 DI3 DI2 ...
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... UOSEL is impossible. In case of setting with PBSEL at 0, the setting for EMPHA/UO/CO terminal follows the setting for UOSEL. • The setting of AOSEL comes into effect in the case that the bit 1 output of channel status is selected with VOSEL. In the case that 1 is selected with AOSEL, IEC61937, non-PCM synchronous signal is detected. LC89057W-VF4A-E DI5 DI4 DI3 0 1 ...
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... Since the fs calculation is always done when the oscillation amplifier is set to the permanent continuous operation mode, fs changes are always reflected to the error flag. LC89057W-VF4A-E DI5 DI4 ...
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... Setting of RLRCK output frequency during XIN source 00: 48kHz output (initial value) 01: 96kHz output 10: 192kHz output 11: Muted • If the RMCK frequency is set lower than RBCK when the XIN source is used, 3.072MHz is output from RBCK. This also applies to SBCK. LC89057W-VF4A-E DI5 DI4 DI3 DI2 ...
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... Setting of SBCK frequency during XIN source 00: 3.072MHz output (initial value) 01: 6.144MHz output 10: 12.288MHz output 11: Muted XSLRCK [1:0] SLRCK output frequency setting during XIN source 00: 48kHz output (initial value) 01: 96kHz output 10: 192kHz output 11: Muted LC89057W-VF4A-E DI4 DI3 DI2 DI12 DI11 DI10 ...
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... XIN source is switched. • If the oscillation amplifier is set to stop automatically when the PLL gets locked, XIN source switching from the PLL locked status is executed after the oscillation is stabilized. Moreover, switching of output data at this time is subject to XIN source switching. LC89057W-VF4A-E DI5 DI4 DI3 DI2 ...
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... ROSEL[2:0] selection data output (initial value) 1: "L" fixed output • ULSEL can be set when the oscillation amplifier is set to the permanent continuous operation mode with AMPOPR[1:0]. ULSEL does not work correctly when the oscillation amplifier is stopped. LC89057W-VF4A-E DI5 DI4 DI3 DI2 ...
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... L-channel data; "H" period: R-channel data (initial value) 1: "L" period: R-channel data; "H" period: L-channel data • The data output format and RLRCK output polarity could be set independently. Set the RLRCH polarity in line with each data output format. LC89057W-VF4A-E DI5 DI4 DI3 DI2 ...
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... If these data are identical, it outputs a flag, considering the data has been updated. • The burst preamble Pc update flag also compares the 16 bits of data of the previous block with those of the current data. If they are identical, an update flag is output. LC89057W-VF4A-E DI5 DI4 DI3 ...
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... ERWT[1:0] defines the interval of time for RERR to output error cancellation ("L") after PLL is locked. Since demodulated audio data is output after RERR cancels an error, you need to change this setting if the situation that the head of data is missing is a problem. LC89057W-VF4A-E DI5 DI4 ...
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... Data input when general-purpose I/O PIO2 output is set 0: Output L (initial value) 1: Output H PI3 Data input when general-purpose I/O PIO3 output is set 0: Output L (initial value) 1: Output H • When you use general-purpose I/O PIO0 to PIO3 as output, set PIOEN to "L". LC89057W-VF4A-E DI5 DI4 DI3 DI2 ...
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... In case of inputting 256fs clock into TMCK, the falling edge of TBCK should be in synchronized with the rising edge of TMCK. Also, in case of inputting 128fs clock into TMCK, the falling edge of TBCK is in synchronized with the falling of TMCK. LC89057W-VF4A-E DI5 DI4 DI3 DI2 ...
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... DI21 Bit 13 DI22 Bit 14 DI23 Bit 15 DI24 Bit 16 DI25 Bit 17 DI26 Bit 18 DI27 Bit 19 LC89057W-VF4A-E DI6 Bit 0 to bit 7 1 Bit 0 to bit 15 1 Bit 0 to bit 23 1 Bit 0 to bit 31 1 Description Register Lower chip address DI28 Higher chip address ...
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... DO12 OUNPCM DO13 OPCRNW DO14 DO15 DO16 DO17 IEC1937 DO18 DO19 DO20 DO21 DO22 DO23 DO24 … DO46 DO47 LC89057W-VF4A-E Table 12.5 Read Register Map 0xEA 0xEB PO0 PO1 PO2 PO3 FSC0 FSC1 FSC2 FSC3 FSDAT0 OINDET FSDAT1 FSDAT2 FSDAT3 FSDAT4 FSDAT5 ...
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... Input data exist in RX6 RXDET7 Data detection of modulation function output TXO 0: No data in modulation function output TXO 1: Data exist in modulation function output TXO • For readout of RXDET[7:0], RXMON must be set to "H" beforehand. LC89057W-VF4A-E DO5 DO4 DO3 RXDET5 RXDET4 RXDET3 DO2 ...
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... Channel status emphasis detection (output of status during readout pre-emphasis 1: 50/15μs pre-emphasis exists • Concerning OERROR and OUNPCM, the status of RERR and _______ are read regardless of the INToutput setting. LC89057W-VF4A-E DO13 DO12 DO11 OPCRNW OUNPCM OCSRNW ____________ AUDIO that are subject to RESEL and AOSEL setting ...
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... DTS-CD/LD IEC60958 frame interval 0: Sync signal is not 2048 nor 4096 frame interval 1: Sync signal is 2048 or 4096 frame interval F4096 DTS-CD/LD IEC60958 frame interval 0: Sync signal is not 4096 frame interval 1: Sync signal is 4096 frame interval LC89057W-VF4A-E DO20 DO19 DO18 F0512 DTSES DTS51 ...
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... LC89057W-VF4A-E DO5 DO4 DO3 FSC1 FSC0 PO3 FSC0 Target Frequency 0 0 Out of range 16kHz 0 1 22.05kHz 1 0 24kHz 1 1 32kHz 0 0 44.1kHz ...
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... Bit 15 DO16 Bit 16 Source number DO17 Bit 17 DO18 Bit 18 DO19 Bit 19 DO20 Bit 20 Channel number DO21 Bit 21 DO22 Bit 22 DO23 Bit 23 LC89057W-VF4A-E DO13 DO12 DO11 FSDAT5 FSDAT4 FSDAT3 Contents Register DO24 DO25 DO26 DO27 DO28 DO29 DO30 DO31 DO32 DO33 DO34 ...
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... DO6 DO7 0 1 DO12 to 8 DO15 LC89057W-VF4A-E Table 12.8 Burst Preamble Pc Read Registers Register Bit No. Contents DO0 Bit 0 Data type DO1 Bit 1 DO2 Bit 2 DO3 Bit 3 DO4 Bit 4 DO5 Bit 5 Reserved DO6 ...
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... Table 13.1 Recommended Circuit Parameters (∗∗: See Section 10.1.1) Element Symbol Recommended Parameter Cc 0.1μF Rp 10kΩ C1 1pF to 33pF Rf 1MΩ Rd 220Ω Ci 0.1μF Ri 75Ω ∗∗ C0 ∗∗ C1 ∗∗ R0 LC89057W-VF4A-E Microcontroller ...
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... SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of November, 2007. Specifications and information herein are subject to change without notice. LC89057W-VF4A-E PS No.7202-59/59 ...