LC89057W-VF4A-E SANYO [Sanyo Semicon Device], LC89057W-VF4A-E Datasheet - Page 40

• Manufacturer Part Number: LC89057W-VF4A-E
• Description: Digital Audio Interface Transceiver
• Manufacturer: SANYO [Sanyo Semicon Device]

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If the PLL is stopped with PLLOPR while the PLL is locked, the output clocks are all muted and this muted status
If the permanent continuous operation is set with AMPOPR[1:0] while the PLL is locked, RERR goes to into the error
When an automatic stop mode of the oscillation amplifier is set with AMPOPR[1:0], and if the input fs changes within
continues even if the PLL is unlocked.
status once. It is possible to set the operation with maintaining the RERR status, if a setting with which even a
changed fs is not regarded as an error due to the PLL status is made with FSERR.
the PLL capture range and no lock error occurs, fs is not calculated with the oscillation amplifier stopped. For this
reason, the input data fs and the fs calculation result may not be identical. However, if the channel status fs
information is rewritten in line with input data changes, this information is reflected to the error flag and fs calculation
of the input data is carried out. Since the fs calculation is always done when the oscillation amplifier is set to the
permanent continuous operation mode, fs changes are always reflected to the error flag.
PLLSEL
XINSEL
XMSEL [1:0]
PLLOPR
EXSYNC
AMPOPR [1:0]
AMPOPR1
DI15
DI7
0
CCB address: 0xE8; Command address: 2; Demodulation function: Master clock setting
AMPOPR0
DI14
DI6
0
PLL lock frequency setting
0: 512fs (fs ≤ 96kHz commend) (initial value)
1: 256fs
XIN input frequency setting
0: 12.288MHz (initial value)
1: 24.576MHz
XMCK output frequency setting
00: 1/1 of XIN input frequency (initial value)
01: 1/2 of XIN input frequency
10: Reserved
11: Muted
PLL (VCO) operation setting
0: Operate (initial value)
1: Stop
Setting of PLL unused demodulation (external synchronization)
0: PLL used normal operation (initial value)
1: PLL unused external synchronization operation (supply 256fs clock to TMCK)
Oscillation amplifier operation setting
00: Automatic stopping of oscillation amplifier while PLL is locked (initial value)
01: Permanent continuous operation
10: Reserved
11: Stop
EXSYNC
DI13
DI5
1
LC89057W-VF4A-E
PLLOPR
DI12
DI4
0
XMSEL1
DI11
DI3
0
XMSEL0
DI10
DI2
0
XINSEL
CAU
DI1
DI9
PLLSEL
CAL
DI0
DI8
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