LC89057W-VF4A-E SANYO [Sanyo Semicon Device], LC89057W-VF4A-E Datasheet - Page 50

• Manufacturer Part Number: LC89057W-VF4A-E
• Description: Digital Audio Interface Transceiver
• Manufacturer: SANYO [Sanyo Semicon Device]

12.2.3 Channel status data write
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For channel status data write with the modulation function, set the CCB address to 0xE9.
DI0 to DI7 are not channel status bits. Be sure to input a chip address to DI0 and DI1. Input "0" to DI2, DI3, and DI7
After CE rises, input a clock combined DI0 to DI7 and write data length to CL clock to make CE “L”. For example, if
Input data is written from preamble B where CE has become "L".
because they are reserved by the system. Write length of the channel status data is determined with DI4 to DI6. This
setting is possible up to 48 bits in units of 8 bits.
you write data up to the bit 15 by DI4 to DI6, CL must be 24 clocks while CE is rising. If this setting goes wrong,
correct writing is not expected.
DI6
0
0
0
0
Register
DI10
DI11
DI12
DI13
DI14
DI15
DI16
DI17
DI18
DI19
DI20
DI21
DI22
DI23
DI24
DI25
DI26
DI27
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DI9
Table 12.4 Input Setting -Setting of Modulation Function Channel Status Data- (CCB address : 0xE9)
DI5
0
0
1
1
Table 12.3 Relation between Setting Register of Input Data Length and Data Length
Bit No.
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
DI4
CAU
CAL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
0
1
0
1
0
0
0
0
0
0
Feasible Data Range for Input
Higher chip address
Lower chip address
Data length setting
Bit 0 to bit 15
Bit 0 to bit 23
Bit 0 to bit 31
Bit 0 to bit 7
Source number
Category code
Description
Not defined
Application
Reserved
Reserved
Control
LC89057W-VF4A-E
DI6
1
1
1
1
Register
DI28
DI29
DI30
DI31
DI32
DI33
DI34
DI35
DI36
DI37
DI38
DI39
DI40
DI41
DI42
DI43
DI44
DI45
DI46
DI47
DI48
DI49
DI50
DI51
DI52
DI53
DI54
DI55
DI5
0
0
1
1
Bit No.
DI4
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
Bit 32
Bit 33
Bit 34
Bit 35
Bit 36
Bit 37
Bit 38
Bit 39
Bit 40
Bit 41
Bit 42
Bit 43
Bit 44
Bit 45
Bit 46
Bit 47
0
1
0
1
Feasible Data Range for Input
Sampling frequency
Bit 0 to bit 39
Bit 0 to bit 47
Channel number
Reserved
Reserved
Clock accuracy
Word length
Not defined
Not defined
Description
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