MAX11666AUB+ Maxim Integrated, MAX11666AUB+ Datasheet - Page 24

• Manufacturer Part Number: MAX11666AUB+
• Description: Analog to Digital Converters - ADC 1/2Ch 12-Bit 500ksps Low Power SPI
• Manufacturer: Maxim Integrated

Specifications of MAX11666AUB+

• Rohs: yes
• Number Of Channels: 2
• Architecture: SAR
• Conversion Rate: 500 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Interface Type: SPI
• Operating Supply Voltage: 2.2 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX-10
• Maximum Power Dissipation: 707.3 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.2 V to 3.6 V

500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
The MAX11662/MAX11664/MAX11666 feature dual-input
channels. These devices use a channel-select (CHSEL)
input to select between analog input AIN1 (CHSEL = 0)
or AIN2 (CHSEL = 1). As shown in Figure 13, the CHSEL
signal is required to change between the 2nd and 12th
clock cycle within a regular conversion to guarantee
proper switching between channels.
The ICs can operate with 14 cycles per conversion.
Figure 14 shows the corresponding timing diagram.
Observe that DOUT does not go into high-impedance
mode. Also, observe that t
long to guarantee proper settling of the analog input
voltage. See the Electrical Characteristics table for t
requirements and the Analog Input section for a descrip-
tion of the analog inputs.
Figure 13. Channel Select Timing Diagram
Figure 14. 14-Clock Cycle Operation
24
CHSEL
DOUT
SCLK
DOUT
SCLK
CS
CS
_____________________________________________________________________________________
1
1
0
2
3
2
4
(MSB)
D11
14-Cycle Conversion Mode
5
Dual-Channel Operation
3
6
DATA CHANNEL AIN1
ACQ
D10
7
needs to be sufficiently
8
4
9
D9
10
5
11
D8
12
6
13
14
D7
ACQ
15
7
1/f
t
16
CONVERT
D6
SAMPLE
8
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the ADC package. Noise in the V
power supply, OVDD, and REF affects the ADC’s perfor-
mance. Bypass the V
0.1FF and 10FF bypass capacitors. Minimize capacitor
lead and trace lengths for best supply-noise rejection.
It is important to match the settling time of the input
amplifier to the acquisition time of the ADC. The conver-
sion results are accurate when the ADC samples the
input signal for an interval longer than the input signal’s
worst-case settling time. By definition, settling time is
the interval between the application of an input voltage
step and the point at which the output signal reaches
D5
1
9
2
D4
3
Layout, Grounding, and Bypassing
10
4
Applications Information
5
D3
DATA CHANNEL AIN2
6
Choosing an Input Amplifier
11
DD
7
, OVDD, and REF to ground with
D2
8
12
9
10
D1
13
11
12
D0
t
13
ACQ
14
14
0
15
1
16
0
DD