MAX11332ATJ+ Maxim Integrated, MAX11332ATJ+ Datasheet
MAX11332ATJ+
Specifications of MAX11332ATJ+
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MAX11332ATJ+ Summary of contents
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ADCs with Post-Mux External Signal Conditioning Access General Description The MAX11329–MAX11332 are 12-/10-bit with external reference and 500kHz, full-linear-bandwidth, high-speed, low-power, serial-output successive approximation reg- ister (SAR) analog-to-digital converters (ADCs). The MAX11329–MAX11332 provide external access to the ...
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... Signal-to-Noise Ratio Total Harmonic Distortion (Up to the 5th Harmonic) Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Maxim Integrated Continuous Power Dissipation (T TQFN (derate 34.4mW/NC above +70NC)..................2758mW Operating Temperature Range ........................ -40NC to +125NC + 0.3V) and +4V DD Junction Temperature .....................................................+150NC Storage Temperature Range ............................ -65NC to +150NC ( ...
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... EXTERNAL REFERENCE INPUT REF- Input Voltage Range REF+ Input Voltage Range REF+ Input Current DIGITAL INPUTS (SCLK, DIN, CS, CNVST) Input Voltage Low Input Voltage High Input Hysteresis Maxim Integrated MAX11329–MAX11332 = 3Msps 48MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL CONDITIONS -0 ...
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... SCLK Duty Cycle SCLK Fall to DOUT Transition 16th SCLK Fall to DOUT Disable 14th SCLK Fall to DOUT Disable SCLK Fall to DOUT Enable DIN to SCLK Rise Setup SCLK Rise to DIN Hold Maxim Integrated MAX11329–MAX11332 = 3Msps 48MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) ...
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... DYNAMIC PERFORMANCE (100kHz, input sine wave) (Notes 3 and 7) Signal-to-Noise Plus Distortion Signal-to-Noise Ratio Total Harmonic Distortion (Up to the 5th Harmonic) Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Maxim Integrated = 3Msps 48MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL CONDITIONS ...
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... Static Input Leakage Current Input Capacitance EXTERNAL REFERENCE INPUT REF- Input Voltage Range REF+ Input Voltage Range REF+ Input Current DIGITAL INPUTS (SCLK, DIN, CS, CNVST) Input Voltage Low Input Voltage High Maxim Integrated = 3Msps 48MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL CONDITIONS -0 ...
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... TIMING CHARACTERISTICS (Figure 1) (Note 11) SCLK Clock Period SCLK Duty Cycle SCLK Fall to DOUT Transition 16th SCLK Fall to DOUT Disable 14th SCLK Fall to DOUT Disable SCLK Fall to DOUT Enable DIN to SCLK Rise Setup Maxim Integrated = 3Msps 48MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL ...
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... Figure 3 (Equivalent Input Circuit). Note 11: Guaranteed by characterization CSS 1ST SCLK CLOCK DIN t DOE DOUT Figure 1. Detailed Serial-Interface Timing Diagram Maxim Integrated = 3Msps 48MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL CONDITIONS CSS t CSH t See Figure 6 CSW ...
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... TEMPERATURE (°C) THD vs. ANALOG INPUT FREQUENCY - 3Msps SAMPLE -75 -80 -85 - (kHz) IN Maxim Integrated Typical Operating Characteristics = +25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 1 3Msps SAMPLE 0.5 0 -0.5 -1.0 4096 0 1024 2048 DIGITAL OUTPUT CODE (DECIMAL) HISTOGRAM FOR 30,000 CONVERSIONS ...
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... SAMPLE 5.5 5.0 4.5 4.0 3.5 3.0 -40 -25 - TEMPERATURE (°C) Maxim Integrated Typical Operating Characteristics (continued) = +25°C, unless otherwise noted.) SINAD vs. INPUT RESISTANCE 3Msps SAMPLE f = 100kHz IN 72 BUFFER BETWEEN AOP AND AIP BUFFER BETWEEN AON AND AIN 71 AOP SHORTED TO AIP AON SHORTED TO AIN ...
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... CHANNEL) (8 CHANNEL) 29–32 , 1–10 — — 29–32, 1– — — — — 16 17, 19 5–10, 17 Maxim Integrated REF-/AIN15 15 CNVST/AIN14 14 AIN AIP 13 12 AON 11 AOP 10 AIN13 9 AIN12 TQFN NAME AIN0– ...
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... Maxim Integrated MAX11329–MAX11332 NAME Power-Supply Input. Bypass to GND with a 10FF in parallel with a 0.1FF V DD capacitors. SCLK Serial Clock Input. Clocks data in and out of the serial interface. Active-Low Chip Select Input. When CS is low, the serial interface is enabled. ...
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... ADCs with Post-Mux External Signal Conditioning Access AIN0 AIN1 AIN2 AIN3 AIN(N-1) AIN(N) Maxim Integrated HIGH-INPUT IMPEDANCE PGA/FILTER/BUFFER AOP AON AIN AIP SINGLE- ENDED/ OSCILLATOR DIFFERENTIAL BUS I/P MUX MAX11329–MAX11332 MAX11329–MAX11332 Functional Diagrams REF+ REF- REF- REF+ ...
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... The MAX11329–MAX11332 include internal clock. The internal clock mode features an integrated FIFO, allowing data to be sampled at high speed and then held for read- out at any time lower clock rate. Internal averaging Maxim Integrated AOP AON AIN AIP ...
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... DOUT Ch[3] Ch[2] Ch[1] Ch[0] Figure 2b. External Clock Mode Timing Diagram with CHAN_ID=1 for Best Performance Maxim Integrated MAX11329–MAX11332 mode to generate the serial clock signal. Select the SCLK frequency of 48MHz or less, and set clock polarity (CPOL) and phase (CPHA) in the control registers to the same value. The MAX11329– ...
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... DC signal applied to the REF-/AIN15. Fully Differential Reference (REF+, REF-) When the reference is used in fully differential mode (REFSEL = 1), the full-scale range is set by the difference between REF+ and REF-. The output code reaches its Maxim Integrated ...
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... Table 3. See the Applications Information more detail on programming modes. Maxim Integrated OUTPUT CODE (hex -1.5 LSB Figure 5. Bipolar Transfer Function for 12-Bit Resolution Apply a soft reset when changing from internal to exter- nal clock mode: RESET [1:0] = 10. The MAX11329– ...
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... RESULTS STORED IN FIFO Figure 6. Internal Conversions with CNVST CS EOC SCLK 1 SET MODE REG DIN DOUT MODE CONTROL Figure 7. Internal Conversions with SWCNV Maxim Integrated 1 SET MODE REG READ DATA FROM FIFO INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS 17 SWCNV = 1 INTERNAL OSCILLATOR ON SCAN OPERATION AND RESULTS STORED IN FIFO MAX11329– ...
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... The manual mode works with the external clock only. The FIFO is unused. CS DIN DOUT Figure 8. Echo Back the Configuration Data Maxim Integrated Repeat scanning channel N for number of times and (Table 2). For proper store all the conversion results in the FIFO. The number of scans is programmed in the ADC Configuration register. ...
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... T S Figure 9. SampleSet Use-Model Example Maxim Integrated the ADC allowing both high- and low-frequency inputs to be converted appropriately without interface activity. With the unique sequence loaded into ADC memory, the pattern may be repeated indefinitely or changed at any time. For example, the maximum throughput of MAX11329– ...
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... CHSEL[3:0] 10:7 0000 RESET[1:0] 6:5 Maxim Integrated When the Unipolar or Bipolar registers are configured as pseudo-differential or fully differential, the analog input pairs are repeated in this automated mode. For example set scan all 16 channels and all analog input pairs are configured for fully-differential conversion, the ADC converts the channels twice ...
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... Maxim Integrated Power Management Modes (Table 5). In external clock mode, PM[1:0] selects 00 between normal mode and various power-down modes of operation. External Clock Mode. Channel address is always present in internal clock mode. 0 Set to 1, DOUT is a 16-bit data word containing a 4-bit channel address, followed by a 12-bit conversion result led by the MSB ...
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... Maxim Integrated MODE NAME Scans channels 0 through N Clock mode: External clock only 0 Standard_Ext Channel scan/sequence: N channels in ascending order Channel selection: See Table 4, CHSEL[3:0] determines channel N Averaging: No Scans channel N through the highest numbered channel. The FIFO stores X conversion results where Channel 16– ...
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... Maxim Integrated MODE NAME Scans preprogrammed channel sequence with maximum length of 256. There is no restriction on the channel pattern. Clock mode: External clock only 1 SampleSet Channel scan/sequence: Unique channel sequence Maximum depth: 256 conversions Channel Selection: See Table 4 Averaging: No Continue to operate in the previously selected mode ...
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... Table 6. ADC Configuration Register BIT NAME BIT CONFIG_SETUP 15:11 REFSEL 10 AVGON 9 Maxim Integrated U Full shutdown where all circuitry is shutdown. U Partial shutdown where all circuitry is powered down Table 1 details the When the PM_ bits in the ADC Mode Control register are through Table 14 asserted edge the next frame ...
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... ADCs with Post-Mux External Signal Conditioning Access Table 6. ADC Configuration Register (continued) BIT NAME BIT NAVG[1:0] 8:7 NSCAN[1:0] 6:5 SPM[1:0] 4:3 ECHO 2 — 1:0 Maxim Integrated DEFAULT STATE Valid for internal clock mode only. AVGON NAVG1 Scans channel N and returns results. Valid for repeat mode only. ...
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... SampleSet Mode of Operation The SampleSet register stores the unique channel sequence length. The sequence pattern is comprised 256 unique single-ended and/or differential conver- sions with any order or pattern. Maxim Integrated DEFAULT STATE N/A Set to 10011 to select the RANGE register Set to 0 for AIN0/1: +V ...
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... UNIPOLAR REGISTER BIT NAME UCH0 AIN0 Selection: 1 CHSEL[3:0] = 0000 CHSCAN0 = AIN1 Selection: 1 CHSEL[3:0] = 0001 CHSCAN1 = Maxim Integrated SUPPORTED WAVEFORMS REFSEL = 0 REF+ RANGE IN+ REF+ REF+ GND, AIN15 PDIFF_COM = 1 REF+ RANGE IN+ REF+ REF+ ...
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... BCH10/11 5 BCH12/13 4 BCH14/15 3 — 2:0 Maxim Integrated STATE — Set to 10001 to select the Unipolar register. Set configure AIN0 and AIN1 for pseudo-differential conversion. 0 Set configure AIN0 and AIN1 for single-ended conversion. Set configure AIN2 and AIN3 for pseudo-differential conversion. ...
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... BIT NAME BIT DEFAULT STATE SMPL_SET 15:11 SEQ_LENGTH 10:3 — 2:0 Maxim Integrated — Set to 10100 to select the Custom Scan0 register. 0 Set scan AIN15. Set omit AIN15. 0 Set scan AIN14. Set omit AIN14. 0 Set scan AIN13. Set omit AIN13. ...
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... For best performance, use PCBs with a solid ground plane. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or digital lines underneath the ADC package. Noise in the V Maxim Integrated MAX11329–MAX11332 16 1 ENTRY 1 ...
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... BIPOLAR REGISTER SET PER REGISTER SET BIT PDIFF_COM CHANNEL UCH{X}/{X+ FOR PSEUDO- AND BCH{X}/{X+ FOR DIFFERENTIAL SELECTION SINGLE-ENDED SELECTION Figure 11. ADC Programming Sequence Maxim Integrated SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL SELECT ADC FIGURE OUT NUMBER OF CHANNELS TO USE (N) FOR EACH ADC CHANNEL ...
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... ADC CONFIGURATION REGISTER YES UPPER-INT NO ADC CONFIGURATION REGISTER YES CUSTOM-INT NO ADC CONFIGURATION REGISTER Figure 12. ADC Mode Select Programming Sequence Maxim Integrated INTERNAL INTERNAL/EXTERNAL CLOCK NO AVERAGE YES SET AVG ON BIT TO 1 SET NAVG[1: ADC CONFIGURATION REGISTER SET NSCAN[1:0] FOR SCAN COUNT ...
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... INPUT 1 MAX4430 0.1µF 500I 4 5 INPUT 2 MAX4430 0.1µF Figure 13. Typical Application Circuit Maxim Integrated U Initial voltage accuracy U Temperature drift U Current source capability U Current sink capability U Quiescent current U Noise. See +5V 0.1µF 10µ 100pF 0.1µF 10µF 500I 10I 1 ...
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... High precision, wide temperature range MAX6129B Low cost, ultra-low power MAX6003 Low cost, low power Maxim Integrated Definitions In reality, there are other noise sources besides quantiza- tion noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio ...
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... PART PIN-PACKAGE MAX11329ATJ+ 32 TQFN-EP* MAX11330ATJ+ 32 TQFN-EP* MAX11331ATJ+ 32 TQFN-EP* MAX11332ATJ+ 32 TQFN-EP* Note: All devices are specified over the -40°C to +125°C temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Maxim Integrated MAX11329–MAX11332 PROCESS: BiCMOS Ordering Information ...
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... Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 2012 Maxim Integrated © MAX11329–MAX11332 DESCRIPTION The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc. Revision History PAGES CHANGED — 36 ...