MAX11332ATJ+ Maxim Integrated, MAX11332ATJ+ Datasheet - Page 15

• Manufacturer Part Number: MAX11332ATJ+
• Description: Analog to Digital Converters - ADC MAX11332ATJ+
• Manufacturer: Maxim Integrated

Specifications of MAX11332ATJ+

• Rohs: yes
• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 3 MSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 72.3 dB
• Interface Type: 3-Wire, QSPI, SPI
• Operating Supply Voltage: 1.5 V to 3.6 V, 2.35 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-32
• Maximum Power Dissipation: 2758 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1

in single-ended or differential configuration. The external
buffering stage should be designed to properly drive the
input sampling network of the ADC.
The external buffer should also have very high input
impedance (low-leakage current) to ensure best linearity.
If additional signal processing is not required, connect
AOP to AIP and AON to AIN. It is recommended to limit
the source impedance to not affect the sampling accu-
racy of the ADC causing degradation in linearity and total
harmonic distortion. See the SINAD vs. Input Resistance
graph in the
The ADC’s input-tracking circuitry features a 500MHz
small-signal full-linear bandwidth to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. Anti-alias filtering of the input
signals is necessary to avoid high-frequency signals
aliasing into the frequency band of interest.
The MAX11329–MAX11332 feature a serial interface
compatible with SPI/QSPI and MICROWIRE devices. For
SPI/QSPI, ensure the CPU serial interface runs in master
Figure 2a. External Clock Mode Timing Diagram with CHAN_ID=1
Figure 2b. External Clock Mode Timing Diagram with CHAN_ID=1 for Best Performance
Maxim Integrated
DOUT
SCLK
DOUT
SCLK
DIN
DIN
CS
CS
Typical Operating
Post-Mux External Signal Conditioning Access
1
1
Ch[3]
Ch[3]
DI[15]
DI[15]
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
2
2
Ch[2]
Ch[2]
DI[14]
3
3
Ch[1] Ch[0]
Ch[1] Ch[0]
3-Wire Serial Interface
Characteristics.
4
4
Input Bandwidth
5
5
MSB MSB-1
MSB MSB-1
6
6
7
7
8
8
9
9
10
10
mode to generate the serial clock signal. Select the SCLK
frequency of 48MHz or less, and set clock polarity (CPOL)
and phase (CPHA) in the control registers to the same
value. The MAX11329–MAX11332 operate with SCLK
idling high, and thus operate with CPOL = CPHA = 1.
Set CS low to latch input data at DIN on the rising edge
of SCLK. Output data at DOUT is updated on the falling
edge of SCLK. A high-to-low transition on CS samples
the analog inputs and initiates a new frame. A frame is
defined as the time between two falling edges of CS.
There is a minimum of 16 bits per frame. The serial data
input, DIN, carries data into the control registers clocked
in by the rising edge of SCLK. The serial data output,
DOUT, delivers the conversion results and is clocked out
by the falling edge of SCLK. DOUT is a 16-bit data word
containing a 4-bit channel address, followed by a 12-bit
conversion result led by the MSB when CHAN_ID is set
to 1 in the ADC Mode Control register
CHAN_ID is set to 1 keep the SCLK high for at least 25ns
before the CS falling edge
set to 0 (external clock mode only), the 16-bit data word
includes a leading zero and the 12-bit conversion result
is followed by 3 trailing zeros
conversion result is followed by 5 trailing zeros.
11
11
MAX11329–MAX11332
12
12
13
13
14
14
15
15
LSB+1
LSB+1
DI[1]
DI[1]
(Figure
16
16
LSB
DI[0]
LSB
(Figure
DI[0]
2b). When CHAN_ID is
t
QUIET
(Figure
> t
2c). In the 10-bit
SCLK
2a). When
15