MAX11332ATJ+ Maxim Integrated, MAX11332ATJ+ Datasheet - Page 8

• Manufacturer Part Number: MAX11332ATJ+
• Description: Analog to Digital Converters - ADC MAX11332ATJ+
• Manufacturer: Maxim Integrated

Specifications of MAX11332ATJ+

• Rohs: yes
• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 3 MSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 72.3 dB
• Interface Type: 3-Wire, QSPI, SPI
• Operating Supply Voltage: 1.5 V to 3.6 V, 2.35 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-32
• Maximum Power Dissipation: 2758 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1

ELECTRICAL CHARACTERISTICS (MAX11329/MAX11330) (continued)
(V
unless otherwise noted. Typical values are at T
Note 2: Limits are 100% production tested at T
Note 3: Channel ID disabled.
Note 4: Tested in single-ended mode.
Note 5: Offset nulled.
Note 6: Line rejection D(D
Note 7: Tested and guaranteed with fully differential input.
Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.
Note 9: The operational input voltage range for each individual input of a differentially configured pair is from V
Note 10: See
Note 11: Guaranteed by characterization.
Figure 1. Detailed Serial-Interface Timing Diagram
Maxim Integrated
SCLK Rise to DIN Hold
CS Fall to SCLK Fall Setup
SCLK Fall to CS Fall Hold
CNVST Pulse Width
CS or CNVST Rise to EOC Low
(Note 7)
CS Pulse Width
DD
DOUT
SCLK
DIN
CS
= 2.35V to 3.6V, V
Parts are tested with MUX externally connected to the ADC input.
Maximum conversion time: 1.91Fs + N x 16 x t
t
operational input voltage difference is from -V
OSC_MAX
PARAMETER
Post-Mux External Signal Conditioning Access
Figure 3
t
CSS
= 29.4ns, t
t
CLOCK
DOE
1ST
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
OVDD
(Equivalent Input Circuit).
t
DS
OUT
= 1.5V to 3.6V, f
OSC_TYP
) with V
t
DH
SYMBOL
t
CNV_INT
t
DD
t
CSBW
t
t
CSW
t
CSS
CSH
= 25ns.
DH
= 2.35V to 3.6V and V
SAMPLE
t
A
CH
A
See Figure 6
See Figure 7, f
= +25NC.) (Note 2)
= +25NC. Limits over the operating temperature range are guaranteed by design.
= 3Msps, f
REF+
OSC_MAX
/2 to +V
SAMPLE
SCLK
CONDITIONS
REF+
REF+
= 48MHz, 50% duty cycle, V
= 2.35V.
= 3Msps
/2 or -V
t
CP
t
MAX11329–MAX11332
DOT
REF+
to +V
REF+
CLOCK
16TH
t
CSH
.
t
MIN
CSBW
REF+
1
4
1
5
5
= V
TYP
DD
t
1.7
DOD
, T
A
DD
= -40NC to +125NC,
MAX
2.4
to GND. The
UNITS
ns
ns
ns
ns
Fs
ns
8