ZADCS1242IS16T ZMDI, ZADCS1242IS16T Datasheet

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Data Sheet Rev. 2.0 / October 2011 ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family ...

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... The internal clock mode can be used synchronous conversions on several ZMDI ADCs in parallel. The “V” versions ZADCS1282V/ZADCS1242V/ ZADCS1222V are equipped with a high accurate internal 2.5V reference with an additional external ±1.5% voltage adjustment range. ...

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... Battery-Powered Systems  Automotive Ordering Information Order Code 12 8 ZADCS1282VIS20T 12 8 ZADCS1282IS20T 12 4 ZADCS1242VIS16T 12 4 ZADCS1242IS16T 12 2 ZADCS1222VIS14T 12 2 ZADCS1222IS14T Sales and Further Information Zentrum Mikroelektronik ZMD America, Inc. 8413 Excelsior Drive Dresden AG Grenzstrasse 28 Suite 200 01109 Dresden Madison, WI 53717 Germany ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family Contents 1 General Device Specification 1.1. Absolute Maximum Ratings (Non Operating) 1.2. Package Pin Assignment ZADCS1282 / ZADCS1282V 1.3. Package Pin Assignment ZADCS1242 / ZADCS1242V 1.4. Package Pin Assignment ZADCS1222 / ZADCS1222V 1.5. Electrical Characteristics ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family List of Figures Figure 1 Package Pin Assignment for ZADCS1282 & ZADCS1282V........................................................................8 Figure 2 Package Pin Assignment for ZADCS1242 & ZADCS1242V........................................................................9 Figure 3 Package Pin Assignment for ZADCS1222 & ZADCS1222V......................................................................10 Figure 4: Basic application schematic ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family List of Tables Table 1: Absolute Maximum Ratings..........................................................................................................................7 Table 2: Pin list ZADCS1282 / ZADCS1282V ............................................................................................................8 Table 3: Pin list ZADCS1242 / ZADCS1242V ............................................................................................................9 Table 4: Pin list ZADCS1222 / ZADCS1222V ..........................................................................................................10 Table 5: Channel ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family 1 General Device Specification 1.1. Absolute Maximum Ratings (Non Operating) Symbol Parameter V VDD to AGND, DGND DD-GND V AGND to DGND AGND-DGND CH0 – CH7, COM to AGND, DGND VREF, VREFADJ to AGND Digital ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family 1.2. Package Pin Assignment ZADCS1282 / ZADCS1282V Package Name Direction Type pin number 1 nCS IN 2 DIN IN 3 DGND 4 AGND 5 VREF I/O 6 COM IN 7 CH0 IN 8 CH1 IN ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family 1.3. Package Pin Assignment ZADCS1242 / ZADCS1242V Package Name Direction Type pin number 1 nCS IN 2 DIN IN 3 DGND 4 AGND 5 VREF I/O 6 COM IN 7 CH0 IN 8 CH1 IN ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family 1.4. Package Pin Assignment ZADCS1222 / ZADCS1222V Package Name Direction Type pin number 1 nCS IN 2 DIN IN 3 DGND 4 AGND 5 VREF I/O 6 COM IN 7 CH0 IN 8 CH1 IN ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family 1.5. Electrical Characteristics 1.5.1. General Parameters (VDD = +2. 5.25V 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); V SCLK  ) OPmax Parameter DC Accuracy Resolution Relative Accuracy No ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family 1.5.2. Specific Parameters of ZADCS12x2V versions (with Internal Reference) = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps);  (VDD = +2. 5.25V; f SCLK Parameter Internal Reference at VREF VREF Output ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family 1.5.3. Specific Parameters of basic ZADCS12x2 versions (without Internal Reference) = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps);  (VDD = +2. 5.25V; f SCLK Parameter External Reference at VREF VREF ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family 1.6. Typical Operating Characteristics Integral Nonlinearity vs. Code 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0 512 1024 1536 2048 Code IDD vs. VDD 1500 1350 1200 IDDactive (converting) 1050 900 ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family 2 Detailed Description 2.1. General Operation The ZADCS12x2 family is a set of classic successive approximation register (SAR) type converters. The architecture is based on a capacitive charge redistribution DAC merged with a resistor string ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family 2.2. Analog Input The analog input to the converter is fully differential. Both converter input signals IN Block diagram at front page) get sampled during the acquisition period enabling the converter to be used in ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family In bipolar mode, IN can range from (IN + (IN +Vref/2) keeping the converter out of code – saturation. For instance set to a constant DC – voltage of Vref/2, then IN ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family together with the source impedance, it may be useful for certain applications. The small-signal bandwidth of the input tracking circuitry is 3.8MHz. Hence it is possible to digitize high-speed transient events and periodic signals with ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family nCS SCLK UNI/ DIN BIP (Start) Idle SSTRB DOUT Figure 11: 24-Clock External Clock Mode Timing (f nCS SCLK UNI/ SGL/ DIN BIP DIF (Start) ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family nCS SCLK UNI/ SGL/ DIN BIP DIF (Start) Idle SSTRB DOUT Figure 13: 16-Clock External Clock Mode Conversion nCS SCLK PD1 PD0 UNI/ SGL/ DIN ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family Digital Timing In general the clock frequency at SCLK may vary from 0.1MHz to 3.2MHz. Considering all telegram pauses or other interruptions of a continuous clock at SCLK, each conversion must be completed within 1.2ms ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family Output Code Format ZADCS12x2 family devices do all support unipolar and bipolar operation modes. The digital output code is straight binary in unipolar mode. It ranges from 0x00 for an input voltage difference of 0V ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family Hardware Power Down The third power down mode is called Hardware Power-Down initiated by pulling the nSHDN pin LOW. If this condition is true, the device will immediately shut down all circuitry just ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family 3 Layout To achieve optimum conversion performance care must be taken in design and layout of the application board highly recommended to use printed circuit boards instead of wire wrap designs and to ...

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ZADCS1282/1242/1222 12-Bit, 200ksps, ADC Family 4 Package Drawing ZADCS1282 devices are delivered in a 20-pin SSOP-package that has the dimensions as shown in Figure 20 and Table 9. ZADCS1242 and ZADCS1222 devices apply respective 16-pin and 14-pin SSOP-packages. Their dimensions ...

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... Dresden AG, Japan Office 2nd Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan +1 (608) 829-1987 Phone +81.3.6895.7410 +1 (631) 549-2882 Fax +81.3.6895.7301 adc@zmdi.com ZMD FAR EAST, Ltd. 3F, No. 51, Sec. 2, Keelung Road 11052 Taipei Taiwan Phone +886 2 2377 8189 Fax +886 2 2377 8199 ...