ZADCS1242IS16T ZMDI, ZADCS1242IS16T Datasheet - Page 24

• Manufacturer Part Number: ZADCS1242IS16T
• Description: Analog to Digital Converters - ADC ADC
• Manufacturer: ZMDI

Specifications of ZADCS1242IS16T

• Product Category: Analog to Digital Converters - ADC
• Rohs: yes
• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 70 dB
• Interface Type: Microwire, QSPI, SPI
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-16
• Maximum Power Dissipation: 250 mW
• Minimum Operating Temperature: - 25 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

3
To achieve optimum conversion performance care must be taken in design and layout of the application
board. It is highly recommended to use printed circuit boards instead of wire wrap designs and to establish a
single point star connection ground system towards AGND (see Figure 19).
For optimal noise performance the star point should be located very close to the AGND pin of the converter.
The ground return to the power supply should be as short as possible and low impedance.
All other analog ground points of external circuitry that is related to the A/D converter as well as the DGND pin
of the device should be connected to this ground point too. Any other digital ground system should be kept
apart as far as possible and connect on the power supply point only.
Analog and digital signal domains should also be separated as well as possible and analog input signals
should be shielded by AGND ground planes from electromagnetic interferences. Four-layer PCB boards that
allow smaller vertical distances between the ground plane and the shielded signals do generally show a better
performance than two-layer boards.
The sampling phase is the most critical portion of the overall conversion timing for signal distortion. If possible,
the switching of any high power devices or nearby digital logic should be avoided during the sampling phase
of the converter.
Figure 18: Supply Current versus Sampling Rate
The fully differential internal architecture of the ZADCS12x2 family ensures very good suppression of power
supply noise. Nevertheless, the SAR architecture is generally sensitive to glitches or sudden changes of the
power supply that occur shortly before the latching of the comparator output. It is therefore recommended to
bypass the power supply connection very close to the device with capacitors of 0.1µF (ceramic) and >1µF
(electrolytic). In case of a noisy supply, an additional series resistor of 5 to 10 ohms can be used to low-pass
filter the supply voltage. The reference voltage should always be bypassed with capacitors of 0.1µF (ceramic)
and ≥ 4.7µF (electrolytic) as close as possible to the VREF pin. If V
series resistance in the V
current of about 100µA is drawn through the VREF pin that could cause a noticeable voltage drop across the
resistance.
Data Sheet
October 12, 2011
ZADCS1282/1242/1222
12-Bit, 200ksps, ADC Family
10000
1000
100
10
Layout
1
External Clock Mode, External V
1
Current consumption vs. Sample Rate
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
10
Sample Rate (ksps)
REF
supply path can cause a gain error of the converter. During conversion, a DC
REF
, f
100
SCLK
= 3.3MHz
1000
Figure 19: Optimal Power-Supply Grounding System
Other
Digital
Circuitry
ZADCS12x2
Family
REF
DGND
DGND
DVDD
COM
is provided by an external source, any
Optional
R = 10Ω
VDD1
(+2.7 … +5.25V)
GND
VDD2
24 of 26