ZADCS1242VIS16T ZMDI, ZADCS1242VIS16T Datasheet - Page 19

• Manufacturer Part Number: ZADCS1242VIS16T
• Description: Analog to Digital Converters - ADC ADC
• Manufacturer: ZMDI

Specifications of ZADCS1242VIS16T

• Product Category: Analog to Digital Converters - ADC
• Rohs: yes
• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 70 dB
• Interface Type: Microwire, QSPI, SPI
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-16
• Maximum Power Dissipation: 250 mW
• Minimum Operating Temperature: - 25 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

Figure 11: 24-Clock External Clock Mode Timing (f
Figure 12: Internal Clock Mode Timing with interleaved Control Byte transmission
Table 7 Control Byte Format
Data Sheet
October 12, 2011
BIT
7
(MSB)
6
5
4
3
2
1
0 (LSB)
SSTRB
DOUT
ZADCS1282/1242/1222
12-Bit, 200ksps, ADC Family
SSTRB
SCLK
DOUT
SCLK
nCS
DIN
nCS
DIN
Name
START
A2
A1
A0
UNI/BIP
SGL/DIF
PD1
PD0
(Start)
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
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changes without notice.
(Start)
S
1
S
1
A2 A1 A0
Idle
A2 A1 A0
Idle
Description
The Start Bit is defined by the first logic ‘1’ after nCS goes low.
Channel Select Bits. Along with SGL/DIF these bits control the setting of the input multiplexer.
For further details on the decoding see also Table 5 and Table 6.
Output Code Bit. The value of the bit determines conversion mode and output code format.
‘1’
‘0’
Single-Ended / Differential Select Bit. Along with the Channel Select Bits A2 .. A0 this bit
controls the setting of the input multiplexer
‘1’
‘0’
Power Down and Clock Mode Select Bits
PD1
0
0
1
1
UNI/
BIP
UNI/
BIP
=
=
=
PD0
=
0
1
0
1
SGL/
DIF
SGL/
DIF
Acquire
PD1 PD0
Acquire
PD1 PD0
t
ACQ
unipolar - straight binary coding
bipolar - two’s complement coding
single ended - all channels CH0 … CH7 measured referenced to COM
differential - the voltage between two channels is measured
Mode
Full Power-Down
Fast Power-Down
Internal clock mode
External clock mode
8
8
Conversion
t
CONV
1
(MSB)
B11 B10 B9 B8 B7 B6 B5
SCLK
≤ 3.2MHz)
1
(MSB)
B11 B10 B9
Conversion
B8 B8 B6
8
Result Output
B4
1
B5
B3 B2 B1 B0
8
B4
S
1
A2 A1 A0
B3
(LSB)
B2 B1 B0
Zero filled
Idle
(LSB)
UNI/
BIP
SGL/
8
DIF
Zero filled
Acquire
PD1 PD0
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