C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 286

• Manufacturer Part Number: C8051F966-A-GQ
• Description: 8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F966-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
23. Clocking Sources
C8051F96x devices include a programmable precision internal oscillator, an external oscillator drive cir-
cuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision internal
oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 23.1. The external oscillator can be configured using the OSCXCN register. The low power internal
oscillator is automatically enabled and disabled when selected and deselected as a clock source. SmaRT-
Clock operation is described in the SmaRTClock oscillator chapter.
The system clock (SYSCLK) can be derived from the precision internal oscillator, external oscillator, low
power internal oscillator, low power internal oscillator divided by 8, or SmaRTClock oscillator. The global
clock divider can generate a system clock that is 1, 2, 4, 8, 16, 32, 64, or 128 times slower that the selected
input clock source. Oscillator electrical specifications can be found in the Electrical Specifications Chapter.
The proper way of changing the system clock when both the clock source and the clock divide value are
being changed is as follows:
If switching from a fast “undivided” clock to a slower “undivided” clock:
If switching from a slow “undivided” clock to a faster “undivided” clock:
286
VDD
Option 2
1. Change the clock divide value.
2. Poll for CLKRDY > 1.
3. Change the clock source.
1. Change the clock source.
2. Change the clock divide value.
3. Poll for CLKRDY > 1.
XTAL2
Option 1
Option 4
10M
XTAL2
Option 3
XTAL2
XTAL1
XTAL2
Figure 23.1. Clocking Sources Block Diagram
OSCICL
Internal Oscillator
Drive Circuit
Oscillator
Precision
External
OSCXCN
EN
OSCICN
Internal Oscillator
Low Power
Rev. 0.5
8
Low Power Internal Oscillator
Precision Internal Oscillator
SmaRTClock
Oscillator
Oscillator Divided by 8
SmaRTClock Oscillator
Low Power Internal
External Oscillator
CLKSEL
Clock Divider
n
CLKRDY
SYSCLK