C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 216

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

C8051F96x
16. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F96x's resources and peripherals.
The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as imple-
menting additional SFRs used to configure and access the sub-systems unique to the C8051F96x. This
allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set.
Table 16.3 lists the SFRs implemented in the C8051F96x device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing unoccupied addresses in the SFR
space will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the
data sheet, as indicated in Table 16.3, for a detailed description of each register.
16.1. SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory
address space. The SFR memory space has 256 pages. In this way, each memory location from 0x80 to
0xFF can access up to 256 SFRs. The C8051F96x family of devices utilizes two SFR pages: 0x00 and
0x0F. SFR pages are selected using the Special Function Register Page Selection register, SFRPAGE
(see SFR Definition 11.3). The procedure for reading and writing an SFR is as follows:
16.2. Interrupts and SFR Paging
When an interrupt occurs, the current SFRPAGE is pushed onto the SFR page stack. Upon execution of
the RETI instruction, the SFR page is automatically restored to the SFR Page in use prior to the interrupt.
This is accomplished via a three-byte SFR Page Stack. The top byte of the stack is SFRPAGE, the current
SFR Page. The second byte of the SFR Page Stack is SFRNEXT. The third, or bottom byte of the SFR
Page Stack is SFRLAST. Upon an interrupt, the current SFRPAGE value is pushed to the SFRNEXT byte,
and the value of SFRNEXT is pushed to SFRLAST. On a return from interrupt, the SFR Page Stack is
popped resulting in the value of SFRNEXT returning to the SFRPAGE register, thereby restoring the SFR
page context without software intervention. The value in SFRLAST (0x00 if there is no SFR Page value in
the bottom of the stack) of the stack is placed in SFRNEXT register. If desired, the values stored in
SFRNEXT and SFRLAST may be modified during an interrupt, enabling the CPU to return to a different
SFR Page upon execution of the RETI instruction (on interrupt exit). Modifying registers in the SFR Page
Stack does not cause a push or pop of the stack. Only interrupt calls and returns will cause push/pop oper-
ations on the SFR Page Stack.
On the C8051F96x devices, the SFRPAGE must be explicitly set in the interrupt service routine.
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1. Select the appropriate SFR page number using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
Rev. 0.5