74AVCH2T45GF,115 NXP Semiconductors, 74AVCH2T45GF,115 Datasheet - Page 10

• Manufacturer Part Number: 74AVCH2T45GF,115
• Description: Bus Transceivers 3.6V 250mW 15.8ns
• Manufacturer: NXP Semiconductors

Specifications of 74AVCH2T45GF,115

• Rohs: yes
• Propagation Delay Time: 15.8 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 0.8 V
• Maximum Operating Temperature: + 125 C
• Package / Case: XSON-8
• Maximum Power Dissipation: 250 mW
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 5000

NXP Semiconductors
11. Dynamic characteristics
Table 9.
Voltages are referenced to GND (ground = 0 V); for test circuit see
[1]
Table 10.
Voltages are referenced to GND (ground = 0 V); for test circuit see
[1]
Table 11.
Voltages are referenced to GND (ground = 0 V).
[1]
[2]
74AVCH2T45
Product data sheet
Symbol Parameter
t
t
t
Symbol Parameter
t
t
t
Symbol Parameter
C
pd
dis
en
pd
dis
en
PD
t
t
t
t
C
P
f
f
C
V
N = number of inputs switching;
(C
f
pd
en
pd
en
i
o
i
D
CC
PD
= input frequency in MHz;
L
= 10 MHz; V
= output frequency in MHz;
is the same as t
is a calculated value using the formula shown in
is the same as t
is a calculated value using the formula shown in
= load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
 V
propagation delay A to B
disable time
enable time
propagation delay A to B
disable time
enable time
power dissipation
capacitance
PD
Typical dynamic characteristics at V
Typical dynamic characteristics at V
Typical power dissipation capacitance at V
CC
 V
2
 f
CC
I
o
= GND to V
2
) = sum of the outputs.
 f
PLH
PLH
i
 N + (C
and t
and t
CC
PHL
PHL
; t
Conditions
B to A
DIR to A
DIR to B
DIR to A
DIR to B
Conditions
B to A
DIR to A
DIR to B
DIR to A
DIR to B
Conditions
A port: (direction A to B);
B port: (direction B to A)
A port: (direction B to A);
B port: (direction A to B)
L
; t
; t
r
 V
= t
dis
dis
f
CC
is the same as t
is the same as t
= 1 ns; C
2
 f
o
All information provided in this document is subject to legal disclaimers.
) where:
L
= 0 pF; R
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Section 13.4 “Enable times”
Section 13.4 “Enable times”
PLZ
PLZ
CC(A)
CC(B)
Rev. 6 — 2 April 2013
and t
and t
L
=  .
= 0.8 V and T
= 0.8 V and T
D
CC(A)
PHZ
PHZ
in W).
0.8 V
0.8 V
0.8 V
15.8
15.8
12.2
11.7
27.5
28.0
15.8
15.8
12.2
11.7
27.5
28.0
1
9
; t
; t
en
en
= V
is the same as t
is the same as t
CC(B)
Figure
Figure
1.2 V
1.2 V
1.2 V
12.7
12.2
20.6
17.6
20.6
12.7
17.6
amb
8.4
7.9
amb
8.4
4.9
9.2
11
2
and T
8; for wave forms see
8; for wave forms see
= 25 C
= 25 C
amb
V
PZL
PZL
1.5 V
1.5 V
1.5 V
CC(A)
12.4
12.2
20.0
20.2
12.4
17.0
16.2
8.0
7.6
8.0
3.8
9.0
11
2
= 25 C
[1]
[1]
and t
and t
V
V
and V
CC(B)
CC(A)
PZH
PZH
1.8 V
1.8 V
1.8 V
12.2
12.2
20.4
20.2
.
12.2
16.8
15.9
.
[1][2]
8.0
8.2
8.0
3.7
8.8
12
CC(B)
2
74AVCH2T45
Figure 6
Figure 6
2.5 V
2.5 V
2.5 V
12.0
12.2
20.7
20.9
12.0
17.4
14.8
8.7
8.7
8.7
2.8
8.7
14
2
© NXP B.V. 2013. All rights reserved.
and
and
Figure 7
Figure 7
3.3 V
3.3 V
3.3 V
12.2
10.2
22.0
21.7
18.1
15.2
11.8
11.8
9.5
9.5
3.4
8.6
17
2
10 of 27
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
Unit
pF
pF
ns