25LC1024-I/P Microchip Technology, 25LC1024-I/P Datasheet - Page 6

• Manufacturer Part Number: 25LC1024-I/P
• Description: IC EEPROM 1MBIT 20MHZ 8DIP
• Manufacturer: Microchip Technology

Specifications of 25LC1024-I/P

• Memory Size: 1M (128K x 8)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 128 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 20 MHz
• Access Time: 50 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 10 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

25LC1024
2.0
2.1
The 25LC1024 is a 131,072 byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC
microcontrollers. It may also interface with microcon-
trollers that do not have a built-in SPI port by using
discrete I/O lines programmed properly in firmware to
match the SPI protocol.
The 25LC1024 contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25LC1024 in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
TABLE 2-1:
DS22064D-page 6
Instruction Name
WRITE
READ
WREN
WRDI
RDSR
WRSR
RDID
DPD
FUNCTIONAL DESCRIPTION
Principles of Operation
PE
SE
CE
INSTRUCTION SET
Instruction Format
0000 0011
0000 0010
0000 0110
0000 0100
0000 0101
0000 0001
0100 0010
1101 1000
1100 0111
1010 1011
1011 1001
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Set the write enable latch (enable write operations)
Reset the write enable latch (disable write operations)
Read STATUS register
Write STATUS register
Page Erase – erase one page in memory array
Sector Erase – erase one sector in memory array
Chip Erase – erase all sectors in memory array
Release from Deep power-down and read electronic signature
Deep Power-Down mode
®
BLOCK DIAGRAM
HOLD
SCK
WP
SO
CS
SI
I/O Control
STATUS
Register
Logic
Description
V
V
CC
SS
Memory
Control
 2010 Microchip Technology Inc.
Logic
Dec
X
Sense Amp.
R/W Control
Y Decoder
HV Generator
Page Latches
EEPROM
Array