E909.05A61DC ELMOS Semiconductor, E909.05A61DC Datasheet - Page 26

• Manufacturer Part Number: E909.05A61DC
• Description: Processors - Application Specialized Halios multipurpose sensor IC
• Manufacturer: ELMOS Semiconductor

Specifications of E909.05A61DC

• Rohs: yes
• Processor Series: EL16
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 8 MHz
• Data Ram Size: 3 kB
• Operating Supply Voltage: 2.25 V to 2.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Interface Type: I2C, SPI
• Memory Type: Flash, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

PRELIMINARY INFORMATION AUG 02, 2011
Table 6.4.1: Addressing Modes Table
The complete EL16 instruction set consists of 27 core instructions and 24 emulated instructions. The core
instructions are instructions that have unique op-codes decoded by the CPU. The emulated instructions are
instructions that make code easier to write and read, but do not have op-codes themselves, instead they are
replaced automatically by the assembler with an equivalent core instruction. There is no code or performance
penalty for using emulated instruction.
There are three core-instruction formats:
All single-operand and dual-operand instructions can be byte or word instructions by using .B or .W exten-
sions. Byte instructions are used to access byte data or byte peripherals. Word instructions are used to
access word data or word peripherals. If no extension is used, the instruction is a word instruction.
The source and destination of an instruction are defined by the following fields:
Table 6.5.1: source and destination of an instruction
The following tables shows coding table of the 16 bit opcode:
This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
ELMOS Semiconductor AG
Abbr.
src
dst
As
S-reg
Ad
D-reg
B/W
As/Ad
6.5 EL16 Instruction Set
HALIOS® MULTI-PURPOSE OPTICAL SENSOR WITH HIGH LIGHT IMMUNITY
11/-
•
•
•
Dual-operand
Single-operand
Jump
Addressing Mode
Immediate mode
Syntax
#N
Data Sheet 26 / 67
Description
The source operand defined by As and S-reg
The destination operand defined by Ad and D-reg
The addressing bits responsible for the addressing
mode used for the source (src)
The working register used for the source (src)
The addressing bits responsible for the addressing
mode used for the destination (dst)
The working register used for the destination (dst)
Byte or word operation: 0: word operation, 1: byte
operation
Description
The word following the instruction con-
tains the immediate constant N. Indirect
auto-increment mode @PC+ is used.
QM-No.: 25DS0014E.00
E909.05