MCIMX6Q7CVT08AC Freescale Semiconductor, MCIMX6Q7CVT08AC Datasheet - Page 106

• Manufacturer Part Number: MCIMX6Q7CVT08AC
• Description: Processors - Application Specialized i.MX6Q
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6Q7CVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 105
• Mounting Style: SMD/SMT
• Package / Case: FCBGA
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

3
Electrical Characteristics
4.11.11 LVDS Display Bridge (LDB) Module Parameters
The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD
644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits.”
4.11.12 MIPI D-PHY Timing Parameters
This section describes MIPI D-PHY electrical specifications, compliant with MIPI CSI-2 version 1.0,
D-PHY specification Rev. 1.0 (for MIPI sensor port x4 lanes) and MIPI DSI Version 1.01, and D-PHY
specification Rev. 1.0 (and also DPI version 2.0, DBI version 2.0, DSC version 1.0a at protocol layer) (for
MIPI display port x2 lanes).
4.11.12.1 Electrical and Timing Information
106
Differential Voltage Output Voltage
Output Voltage High
Output Voltage Low
Offset Static Voltage
VOS Differential
Output short-circuited to GND
VT Full Load Test
V
V
V
GNDSH
Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
I
LEAK
Symbol
Parameter
Input signal voltage range
Input leakage current
Ground Shift
Input DC Specifications—Apply to DSI_CLK_P/_N and DSI_DATA_P/_N Inputs
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 2
Table 68. LVDS Display Bridge (LDB) Electrical Specification
Parameters
Table 69. Electrical and Timing Information
Symbol
V
ISA ISB With the output common shorted to GND
VTLoad 100  Differential load with a 3.74 k load between
OSDIFF
Tdicu
V
V
Voh
Vol
OD
OS
=
100  Differential load
100  differential load
(0 V Diff—Output High Voltage static)
100  differential load
(0 V Diff—Output Low Voltage static)
Two 49.9  resistors in series between N-P
terminal, with output in either Zero or One state, the
voltage measured between the 2 resistors.
Difference in V
GND and I/O supply voltage
1
-- - T diclk
2
Transient voltage range is limited from -300
mV to 1600 mV
VGNDSH(min) = VI = VGNDSH(max) +
VOH(absmax)
Lane module in LP Receive Mode



ceil
OS
Test Conditions
Test Condition
2
----------------------------------------------- -
between a One and a Zero state
DI_CLK_PERIOD

DISP_CLK_UP
—


Min
-50
-10
-50
Freescale Semiconductor
1.25
1.15
Min
250
247
0.9
-50
-24
Typ
—
—
—
1.375
Max
1.25
450
454
1.6
1350 mV
50
24
Max
10
50
Units
mA
mV
Unit
mV
mV
mV
mA
mV
mV
V