M95040-WDW6TP STMicroelectronics, M95040-WDW6TP Datasheet - Page 13

• Manufacturer Part Number: M95040-WDW6TP
• Description: IC EEPROM 4KBIT 10MHZ 8TSSOP
• Manufacturer: STMicroelectronics

Specifications of M95040-WDW6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Organization: 512 x 8
• Interface Type: SPI
• Maximum Clock Frequency: 5 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8679-2; M95040-WDW6TP

M95040, M95020, M95010
4
4.1
4.2
Operating features
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5
with Serial Clock (C) being low.
Figure 5.
Status register
Figure 6
register contains a number of control bits and status bits, as shown in
description of the Status register bits, see
HOLD
C
also shows what happens if the rising and falling edges are not timed to coincide
shows the position of the Status register in the control logic of the device. This
Hold condition activation
Doc ID 6512 Rev 8
Condition
Hold
Section 6.3: Read Status Register
Figure
5).
Condition
Hold
Table
Operating features
5. For a detailed
(RDSR).
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