CY7C1360C-200AJXC Cypress Semiconductor Corp, CY7C1360C-200AJXC Datasheet - Page 11

• Manufacturer Part Number: CY7C1360C-200AJXC
• Description: IC SRAM 9MBIT 200MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1360C-200AJXC

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3 ns
• Maximum Clock Frequency: 200 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 220 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2125; CY7C1360C-200AJXC

Truth Table
The Truth Table for CY7C1360C and CY7C1362C follows.
Document Number: 38-05540 Rev. *K
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Sleep mode, power-down
READ cycle, begin burst
READ cycle, begin burst
WRITE cycle, begin burst
READ cycle, begin burst
READ cycle, begin burst
READ cycle, continue burst
READ cycle, continue burst
READ cycle, continue burst
READ cycle, continue burst
WRITE cycle, continue burst
WRITE cycle, continue burst
READ cycle, suspend burst
READ cycle, suspend burst
READ cycle, suspend burst
READ cycle, suspend burst
WRITE cycle, suspend burst
WRITE cycle, suspend burst
Notes
6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
7. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
9. CE
10. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
11. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-State when OE is
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
1
, CE
Operation
2
, and CE
3
are available only in the TQFP package. BGA package has only two chip selects CE
Address
External
External
External
External
External
Current
Current
Current
Current
Current
Current
Used
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
CE
H
X
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
L
1
CE
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
2
[6, 7, 8, 9, 10, 11]
CE
H
H
X
X
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
L
3
ZZ ADSP ADSC ADV WRITE OE CLK
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
X
H
H
X
H
H
H
H
X
X
X
H
H
X
X
X
L
L
L
L
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
L
L
L
L
L
1
and CE
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
H
H
L
L
L
L
L
L
X
. Writes may occur only on subsequent clocks
CY7C1360C, CY7C1362C
2
.
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
L
X
L
L
L
X
X
L
L
X
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Page 11 of 34
DQ
Q
Q
Q
Q
Q
Q
D
D
D
D
D
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