M25P20-VMN6TPB NUMONYX, M25P20-VMN6TPB Datasheet - Page 20

• Manufacturer Part Number: M25P20-VMN6TPB
• Description: IC FLASH 2MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P20-VMN6TPB

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Package: 8SO N
• Cell Type: NOR
• Density: 2 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 64KByte x 4
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P20-VMN6TPBTR

6.4
6.4.1
6.4.2
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Figure 9.
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in
Table 6.
The status and control bits of the Status Register are as follows:
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
Status Register Write Protect
S
C
D
Q
SRWD
b7
Status Register Format
Read Identification (RDID) Instruction Sequence and Data-Out Sequence
0
High Impedance
1
0
2
Instruction
3
4
5
0
6
7
MSB
Manufacturer Identification
8
9 10 11 12 13 14 15
0
BP1
Block Protect Bits
MSB
15 14 13
Write Enable Latch Bit
16 17 18
BP0
Device Identification
Figure
3
28 29 30 31
WEL
Write In Progress Bit
2
10.
1
0
AI06809b
WIP
b0