M25PX80-VMN6TP NUMONYX, M25PX80-VMN6TP Datasheet
M25PX80-VMN6TP
Specifications of M25PX80-VMN6TP
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M25PX80-VMN6TP Summary of contents
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... More than 100 000 write cycles per sector More than 20 year data retention Packages – RoHS compliant December 2008 8-Mbit, dual I/O, 4-Kbyte subsector erase, Rev 4 M25PX80 VFQFPN8 (MP) 6 × SO8W (MW) 208 mils SO8N (MN) 150 mils PDIP8 (BA) ...
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... Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13 4.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7.1 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7.2 Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 2/ ...
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Read Status Register (RDSR 6.4.1 ...
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... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity Table 3. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 9. Lock Register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 10 ...
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... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. VFQFPN, SO8, and PDIP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Hold condition activation Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Write Enable (WREN) instruction sequence Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 9 ...
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... Description The M25PX80 Mbit ( serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25PX80 supports two new, high-performance dual input/output instructions: Dual Output Fast Read (DOFR) instruction used to read data MHz using both pin DQ1 and pin DQ0 as outputs ...
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... There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See section for package dimensions, and how to identify pin-1. Package mechanical V CC DQ1 C M25PX80 Function M25PX80 DQ1 2 7 HOLD W ...
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Signal descriptions 2.1 Serial Data output (DQ1) This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). During the Dual Input Fast Program (DIFP) ...
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... If the W/V input is kept in a low voltage range ( input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register. See the range (2) supply. ...
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... Serial Data output (DQ1) line at a time, the other devices are high impedance. Resistors R (represented in ensure that the M25PX80 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high ...
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Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 μs. Figure 4. SPI modes supported CPOL CPHA ...
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... Subsector Erase, Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a subsector at a time, using the Subsector Erase (SSE) instruction, a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction ...
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Active Power, Standby Power and Deep Power-down modes When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PX80 features the following data protection mechanisms: Power On Reset and an internal timer (t inadvertent changes while the power supply is outside the operating specification ...
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... Sector protected from Program/Erase/Write operations Sector protection status cannot be changed except by a Power-up. the second software protected mode (SPM2) uses the Block Protect bits (see Section 6.4.3: BP2, BP1, BP0 allow part of the memory to be configured as read-only. Table 3. Protected area sizes Status Register contents TB ...
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... To restart communication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. 16/60 Memory content Protected area 0 All sectors (16 sectors 15) ...
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Figure 5. Hold condition activation C HOLD (standard use) Hold Condition (non-standard use) Hold Condition AI02029D 17/60 ...
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... Kbytes each) 16 sectors (64 Kbytes each) 4096 pages (256 bytes each) 64 OTP bytes located outside the main memory array Each page can be individually programmed (bits are programmed from 1 to 0). The device is Subsector, Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...
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... Table 4. Memory organization Sector Subsector Address range 255 FF000h 15 240 F0000h 239 EF000h 14 224 E0000h 223 DF000h 13 208 D0000h 207 CF000h 12 192 C0000h 191 BF000h 11 176 B0000h 175 AF000h 10 160 A0000h 159 9F000h 9 144 90000h 143 8F000h 8 128 80000h 127 7F000h ...
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... High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected ...
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Table 5. Instruction set (page Instruction DOFR Dual Output Fast Read Read OTP (Read 64 bytes of ROTP OTP area) Program OTP (Program 64 POTP bytes of OTP area) PP Page Program DIFP Dual Input Fast Program ...
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... Device identification (2 bytes) A Unique ID code (UID) (17 bytes, of which 16 available upon customer request). The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (71h), and the memory capacity of the device in the second byte (14h). ...
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... The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. After this, the 24-bit device identification, stored in the memory, the 8-bit CFD length followed by 16 bytes of CFD content will be shifted out on Serial Data output (DQ1). Each bit is shifted out during the falling edge of Serial Clock (C). ...
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... The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset such cycle is in progress. ...
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SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W/V ) signal. The Status Register Write Disable (SRWD) bit and the Write Protect PP (W/V ) signal allow the device to ...
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... Sector Erase and (HPM) SRWD, BP2, BP1 Bulk Erase and BP0 bits cannot be changed ) is driven High or Low. PP Status Register AI13735 Memory content (1) Unprotected area Ready to accept Page Program and Sector Erase instructions Ready to accept Page Program and Sector Erase instructions Table 8. (1) ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at higher speed (FAST_READ) instruction. ...
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... The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency f during the falling edge of Serial Clock (C) ...
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When the highest address is reached, the address counter rolls over to 00 0000h, so that the read sequence can be continued indefinitely. Figure 14. Dual Output Fast Read instruction sequence S Mode 3 C Mode 2 DQ0 DQ1 S ...
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... OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each bit is latched in on the rising edge of Serial Clock (C). Then the memory contents at that address are shifted out on Serial Data output (DQ1). Each bit is shifted out at the maximum frequency, f (C). The instruction sequence is shown in The address is automatically incremented to the next higher address after each byte of data is shifted out ...
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... Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to ...
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Dual Input Fast Program (DIFP) The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP) instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of only one. ...
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... Program OTP instruction (POTP) The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) bit. ...
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... Bit 0 of the OTP control byte, that is byte 64, (see OTP memory array. When bits and 0 of byte 64 = ’1’, the 64 bytes of the OTP memory array can be programmed. When bits and 0 of byte 64 = ‘0’, the 64 bytes of the OTP memory array are read-only and cannot be programmed anymore. Once a bit of the OTP memory has been programmed to ‘ ...
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Figure 20. How to permanently lock the 64 OTP bytes Byte Byte Byte 6.14 Write to Lock Register (WRLR) The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock Registers. Before it ...
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Table 10. Lock Register in Sector All sectors 1. Values of (b1, b0) after power-up are defined in 6.15 Subsector Erase (SSE) The Subsector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector. Before it can ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
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Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase ...
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Chip Select (S) is driven High, it requires a delay and the Deep Power-down mode is entered. CC2 Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without ...
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Figure 26. Release from Deep Power-down (RDP) instruction sequence S C DQ0 DQ1 42/ Instruction High Impedance Deep Power-down mode t RDP Standby mode AI13745 ...
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Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at power-up, and then for a further delay ...
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Figure 27. Power-up timing (max (min) Reset state of the device V WI Table 11. Power-up timing and V Symbol ( (min low VSL CC (1) t Time delay to ...
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... Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 45/60 ...
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... Fast Program/Erase voltage PP V Electrostatic discharge voltage (Human Body model) ESD 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the Numonyx RoHS compliant 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. Avoid applying V PPH 3. JEDEC Std JESD22-A114A (C1 = 100 pF 1500 Ω 500 Ω). ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...
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Table 16. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep Power-down current CC2 Operating current (READ) I CC3 Operating current (DOFR) Operating current (PP) I CC4 Operating current ...
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Table 17. AC characteristics Test conditions specified in Symbol Alt. Parameter t S active hold time (relative to C) CHSH t S not active setup time (relative to C) SHCH deselect time SHSL CSH ( ...
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When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256). 9. int(A) corresponds to ...
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Expressed as a slew-rate. 5. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’. Figure 29. Serial input timing S tCHSL C tDVCH DQ0 DQ1 Figure 30. Write Protect Setup and Hold timing ...
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Figure 31. Hold timing S C DQ1 DQ0 HOLD Figure 32. Output timing S C tCLQV tCLQX tCLQX DQ1 ADDR. DQ0 LSB IN 52/60 tHLCH tCHHL tCHHH tHLQZ tHHQX tCH tCLQV tCL tQLQH tQHQL tHHCH AI13746 tSHQZ LSB OUT AI13729 ...
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Figure 33. V timing PPH S C DQ0 V PPH V PP tVPPHSL End of command (identi ed by WIP polling) ai13726-b 53/60 ...
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... Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS compliant packages that have have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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Table 19. VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead, 6 × 5 mm, package mechanical data Millimeters Symbol Typ Min R1 0.10 0.00 L 0.60 0.50 Θ aaa bbb ddd Inches Max Typ Min 0.0039 ...
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Figure 35. SO8W 8-lead plastic small outline, 208 mils body width, package outline 1. Drawing is not to scale. Table 20. SO8W 8-lead plastic small outline, 208 mils body width, package mechanical data Symbol Typ 0.40 ...
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Figure 36. SO8N – 8 lead plastic small outline, 150 mils body width, package outline Drawing is not to scale. Table 21. SO8N – 8 lead plastic small outline, 150 mils body ...
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Figure 37. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package outline 1. Package is not to scale. Table 22. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package mechanical data Symbol Typ A ...
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... RoHS compliant 1. Secure options are available upon customer request. 2. Grade 3 is available only in devices delivered in SO8N packages. Note: For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. M25PX80 – 59/60 ...
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... Changes Initial release. Corrected bulk erase specifications on the cover page; Deleted sector 16 from the memory map; Changed Vwi from 2 2 due to 2.3 V operations; threshold on page 44 Corrected the programmable bit range in lock the 64 OTP bytes on page 37. Added the following information regarding Bulk Erase: Avoid applying V to the W/VPP pin during Bulk Erase ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...