XC18V01PC20I Xilinx Inc, XC18V01PC20I Datasheet - Page 3

• Manufacturer Part Number: XC18V01PC20I
• Description: IC PROM SER I-TEMP 3.3V 20-PLCC
• Manufacturer: Xilinx Inc

Specifications of XC18V01PC20I

• Programmable Type: In System Programmable
• Memory Size: 1Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q1153624

Table 1: Pin Names and Descriptions (Continued)
DS026 (v4.1) December 15, 2003
Product Specification
Notes:
1.
2.
3.
V
Name
V
CEO
GND
TMS
TDO
TCK
CCINT
Pin
TDI
NC
CF
CCO
By default, pin 7 is the D4 pin in the 20-pin packages. However, CF --> D4 programming option can be set to override the default and route
the CF function to pin 7 in the Serial mode.
For devices with IDCODES 0502x093h, the input buffers are supplied by V
For devices with IDCODES, 0503x093h, these V
package and pin 20 in 20-pin SOIC and20-pin PLCC packages.
Boundary
R
Order
Scan
22
21
12
11
DATA OUT
DATA OUT
DATA OUT
Function
OUTPUT
OUTPUT
ENABLE
ENABLE
SELECT
DATA IN
CLOCK
MODE
Allows JTAG CONFIG instruction to
initiate FPGA configuration without
powering down FPGA. This is an
open-drain output that is pulsed Low by
the JTAG CONFIG command.
Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the
chain. This output is Low when CE is Low
and OE/RESET input is High, AND the
internal address counter has been
incremented beyond its Terminal Count
(TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
GND is the ground connection.
The state of TMS on the rising edge of
TCK determines the state transitions at
the Test Access Port (TAP) controller.
TMS has an internal 50K ohm resistive
pull-up on it to provide a logic “1” to the
device if the pin is not driven.
This pin is the JTAG test clock. It
sequences the TAP controller and all the
JTAG test and programming electronics.
This pin is the serial input to all JTAG
instruction and data registers. TDI has an
internal 50K ohm resistive pull-up on it to
provide a logic “1” to the system if the pin
is not driven.
This pin is the serial output for all JTAG
instruction and data registers. TDO has
an internal 50K ohm resistive pull-up on it
to provide a logic “1” to the system if the
pin is not driven.
Positive 3.3V supply voltage for internal
logic.
Positive 3.3V or 2.5V supply voltage
connected to the input buffers
output voltage drivers.
No connects.
CCINT
Pin Description
pins are no connects: pin 38 in 44-pin VQFP package, pin 44 in 44-pin PLCC
XC18V00 Series In-System Programmable Configuration PROMs
www.xilinx.com
1-800-255-7778
CCINT
(2)
and
.
6, 18, 28 &
8, 16, 26 &
22, 23, 24,
30, 32, 33,
34, 37, 39,
11, 12, 20,
17, 35 &
44-pin
1, 2, 4,
VQFP
38
10
21
41
31
36
44
5
7
3
(3)
10, 17, 18,
26, 28, 29,
30, 36, 38,
14, 22, 32
39, 40, 43
1, 6, 7, 8,
3, 12, 24
23, 41 &
44-pin
PLCC
44
& 34
& 42
16
27
13
37
11
9
(3)
18 & 20
SOIC &
20-pin
PLCC
7
13
17
19
11
5
6
4
(1)
(3)
3