XC18V01PC20I Xilinx Inc, XC18V01PC20I Datasheet - Page 7

• Manufacturer Part Number: XC18V01PC20I
• Description: IC PROM SER I-TEMP 3.3V 20-PLCC
• Manufacturer: Xilinx Inc

Specifications of XC18V01PC20I

• Programmable Type: In System Programmable
• Memory Size: 1Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q1153624

The read security bit can be set by the user to prevent the
internal programming pattern from being read or copied via
JTAG. When set, it allows device erase. Erasing the entire
device is the only way to reset the read security bit.
Table 3: Data Security Options
IEEE 1149.1 Boundary-Scan (JTAG)
The XC18V00 family is fully compliant with the IEEE Std.
1149.1 Boundary-Scan, also known as JTAG. A Test
Access Port (TAP) and registers are provided to support all
required boundary scan instructions, as well as many of the
optional instructions specified by IEEE Std. 1149.1. In addi-
tion, the JTAG interface is used to implement in-system pro-
gramming (ISP) to facilitate configuration, erasure, and
verification operations on the XC18V00 device.
Table 4
instructions supported in the XC18V00. Refer to the IEEE
Std. 1149.1 specification for a complete description of
boundary-scan architecture and the required and optional
instructions.
Table 4: Boundary Scan Instructions
Instruction Register
The Instruction Register (IR) for the XC18V00 is eight bits
wide and is connected between TDI and TDO during an
DS026 (v4.1) December 15, 2003
Product Specification
Required Instructions
Optional Instructions
XC18V00 Specific Instructions
Boundary-Scan
USERCODE
Program/Erase Allowed
Command
PRELOAD
SAMPLE/
BYPASS
EXTEST
IDCODE
CONFIG
CLAMP
HIGHZ
Default = Reset
Verify Allowed
Read Allowed
lists the required and optional boundary-scan
R
Code [7:0]
00000001
00000000
11111010
11111100
11111101
11101110
11111111
11111110
Binary
Enables BYPASS
Enables boundary-scan
SAMPLE/PRELOAD operation
Enables boundary-scan
EXTEST operation
Enables boundary-scan
CLAMP operation
all outputs in high-impedance
state simultaneously
Enables shifting out
32-bit IDCODE
Enables shifting out
32-bit USERCODE
Initiates FPGA configuration
by pulsing CF pin Low once
Read Inhibited via JTAG
Program/Erase Allowed
Verify Inhibited
Description
Set
XC18V00 Series In-System Programmable Configuration PROMs
www.xilinx.com
1-800-255-7778
instruction scan sequence. In preparation for an instruction
scan sequence, the instruction register is parallel loaded
with a fixed instruction capture pattern. This pattern is
shifted out onto TDO (LSB first), while an instruction is
shifted into the instruction register from TDI. The detailed
composition of the instruction capture pattern is illustrated
in
The ISP Status field, IR(4), contains logic “1” if the device is
currently in ISP mode; otherwise, it contains logic “0”. The
Security field, IR(3), contains logic “1” if the device has been
programmed with the security option turned on; otherwise, it
contains logic “0”.
Figure 3: Instruction Register Values Loaded into IR as
Boundary Scan Register
The boundary-scan register is used to control and observe
the state of the device pins during the EXTEST, SAM-
PLE/PRELOAD, and CLAMP instructions. Each output pin
on the XC18V00 has two register stages that contribute to
the boundary-scan register, while each input pin only has
one register stage.
For each output pin, the register stage nearest to TDI con-
trols and observes the output state, and the second stage
closest to TDO controls and observes the High-Z enable
state of the pin.
For each input pin, the register stage controls and observes
the input state of the pin.
Identification Registers
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be shifted out for examina-
tion by using the IDCODE instruction. The IDCODE is avail-
able to any other system component via JTAG.
The IDCODE register has the following binary format:
where
Note: The LSB of the IDCODE register is always read as
logic “1” as defined by IEEE Std. 1149.1.
Notes:
1. IR(1:0) = 01 is specified by IEEE Std. 1149.1
TDI->
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
Figure
v = the die version number
f = the family code (50h for XC18V00 family)
a = the ISP PROM product ID (36h for the XC18V04)
c = the company code (49h for Xilinx)
IR[7:5]
3.
Part of an Instruction Scan Sequence
0 0 0
Status
IR[4]
ISP
Security
IR[3]
IR[2]
0
IR[1:0]
0 1
->TDO
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