MAX5936ACESA+T Maxim Integrated Products, MAX5936ACESA+T Datasheet - Page 12

• Manufacturer Part Number: MAX5936ACESA+T
• Description: IC HOT-SWAP CTRLR -48V 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Hot-Swap Controllerr

Specifications of MAX5936ACESA+T

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: -10 V ~ -80 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

-48V Hot-Swap Controllers with V
Step Immunity and No R
Figure 9. MAX5936/MAX5937 Normalized Circuit-Breaker
Threshold (V
The power-good outputs, PGOOD (PGOOD), are open
drain and are referenced to V
if V
delay this occurs 1.26ms after the external MOSFET
becomes fully enhanced. PGOOD (PGOOD) deasserts
any time the part enters fault management. PGOOD
(PGOOD) has a delayed response to UVLO. The GATE
goes to V
1.5ms. This turns off the power MOSFET and allows
V
load. PGOOD (PGOOD), in this situation, deasserts
when V
above V
Figure 10. Circuit-Breaker Voltage Margin for High and Low Tempco Power MOSFETS
12
OUT
OUT
______________________________________________________________________________________
to rise depending on the RC time constant of the
OUT
SC
ramps below 72% of V
PGOOD ( PGOOD ) Open-Drain Output
EE
CIRCUIT-BREAKER
TRIP REGION
, whichever occurs first (see Figure 12b).
CB
1.6
1.4
1.2
1.0
0.8
0.6
0.4
rises above V
)
when UVLO is brought below 1.125V for
-40
NORMALIZED MOSFET ON-RESISTANCE
IRF1310NS
NORMALIZED R
-15
T
vs. TEMPERATURE
A
= +25°C
TEMPERATURE (°C)
10
IRFR3910
NORMALIZED R
CB
ON
OUT
R
for more than 1.4ms or
DS(ON)
35
CB
MAX5936/MAX5937
NORMALIZED V
. They assert and latch
TEMPERATURE
, and with the built-in
HIGH TEMPCO
ON
60
I
D
x R
CB
V
CB
DS,ON
85
∆V
CB,MIN
SENSE
Due to the open-drain driver, PGOOD (PGOOD)
requires an external pullup resistor to GND. Due to this
external pullup, PGOOD will not follow positive V
steps as well as if it were driven by an active pullup. As
a result, when PGOOD (PGOOD) is asserted high, an
apparent negative glitch appears at PGOOD (PGOOD)
during a positive V
result of the RC time constant of the external resistor
and the PGOOD pin capacitance lagging the V
It is not due to switching of the internal logic. To mini-
mize this negative transient, it may be necessary to
increase the pullup current and/or to add a small
amount of capacitance from PGOOD (PGOOD) to GND
to compensate for the pin capacitance.
WARNING: For the MAX5936_N/MAX5937_N, PGOOD
(PGOOD) asserts 1.26ms after the power MOSFET is fully
enhanced, independent of V
fully enhanced and UVLO is pulled below its respective
threshold, GATE pulls to V
MOSFET and disconnect the load. When UVLO is
cycled low, PGOOD (PGOOD) is deasserted. In sum-
mary, once the MOSFET is fully enhanced, the
MAX5936_N/ MAX5937_N ignore V
PGOOD (PGOOD) when UVLO goes low or when the
power to the MAX5936_N/ MAX5937_N is fully recy-
cled.
UVLO provides an accurate means to set the turn-on volt-
age level for the MAX5936/MAX5937. Use a resistor-
divider network from GND to V
turn-on voltage (Figure 11). UVLO has hysteresis with a
rising threshold of 1.25V and a falling threshold of 1.125V.
A startup delay of 220ms allows contacts and voltages to
settle prior to initiating the startup sequence (Figure 12a).
CIRCUIT-BREAKER
TRIP REGION
∆V
CB,MIN
Undervoltage Lockout (UVLO)
T
A
= +25°C
IN
IN
step. This negative glitch is a
R
OUT
EE
DS(ON)
TEMPERATURE
. Once the MOSFET is
to turn off the power
EE
LOW TEMPCO
V
I
D
CB
to set the desired
OUT
x R
DS,ON
and deassert
IN
step.
IN