MAX5936ACESA+T Maxim Integrated Products, MAX5936ACESA+T Datasheet - Page 20

• Manufacturer Part Number: MAX5936ACESA+T
• Description: IC HOT-SWAP CTRLR -48V 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Hot-Swap Controllerr

Specifications of MAX5936ACESA+T

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: -10 V ~ -80 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

-48V Hot-Swap Controllers with V
Step Immunity and No R
It is prudent to verify conclusively that all circuit-breaker
and short-circuit faults will be blocked for all ramp
rates. To do this, some form of graphical analysis is
recommended but first, find the value of τ
load by a series of ramp tests as indicated earlier.
These tests include evaluating the load with a series of
V
rate of V
should have a constant slope. The V
must be taken only during the positive ramp. Data
taken after V
must not be used.
Figure 18 shows the load in parallel with the load
capacitor, C
with the power MOSFET, which is fully enhanced with
V
the V
Figure 19 shows the general response of V
ramp over time t. Equation 1 gives the response of V
to a ramp of dV/dt. The product (dV/dt) x τ
∆V
the V
ter of interest is ∆V
necessary to subtract the DC shift in V
load resistance. For some loads, which are relatively
independent of supply voltage, this may be insignificant.
where I
be determined separately with DC tests.
20
Figure 18. V
IN
GS
V
IN
OUT
RAMP
ramps of increasing ramp rates and monitoring the
= 10V. The objective is to determine τ
OUT
IN
___________________________________________________
(max) or the maximum V
LOAD
ramp were to continue indefinitely. The parame-
OUT
response.
V
IN
OUT
LOAD
IN
Ramp Test of Load
is a function of the V
rise during the ramp. Each V
(t) = V
has leveled off at the new higher value
, and the parallel connection in series
OUT
OUT
LOAD CAPACITOR
WITH PARASITICS
due to the ramp dV/dt, thus it is
R
(t) - R
DS,ON
Verification of the Step
10V
DS(ON)
OUT
C
LOAD
OUT
R
EQV
voltage differential if
L
Monitor Timing
EQU
OUT
x I
level that should
OUT
LOAD
response data
OUT
L,eqv
due to the
L,eqv
IN
to a V
LOAD
of the
ramp
from
C
OUT
IN
=
SENSE
At any time (t) the ∆V
If V
time constant of the load is found from:
As mentioned earlier, several measurements of ∆V
at times t1, t2, t3, and t4 should be made during the
ramp. Each of these may result in slightly different val-
ues of τ
In making the measurements, the V
should be such that ∆V
selected ∆V
ramp rates: ∆V
The values of τ
rates due to measurement error, nonlinear dynamics in
the load, and due to the fact that Equation 1 is a simpli-
fication from a higher order dynamic system. The
resulting range of τ
date the performance of the final design.
Having τ
analysis using Equation 1 and Equation 2 can verify the
step monitor function by displaying the relative timing
of t
V
A simple spreadsheet for this purpose can be supplied
by Maxim upon request. Figures 20, 21, and 22 graphi-
cally verify a particular solution over 3 decades of V
ramp rates. In addition, Figure 22 verifies that this solu-
tion will block all circuit-breaker and short-circuit faults
for even the lowest V
exceed V
Figure 19. General Response of V
STEP_MON
CB
VOUTi
OUT
, t
∆V
(t) is measured at time t, then the equivalent
τ
STEP
L,eqv
L,eqv
C
CB
0
OUT
, τ
, and V
.
SC
, and t
L,eqv
and all values should then be averaged.
= -t / ln(1 - ∆V
dv
(t) / [(dV/dt) x τ
dt
t1
SC
V
. The ramp tests should include three
IN
L,eqv
τ
C
RAMP
t2
/ τ
, R
SC
L,eqv
SC
C
IN
OUT
, 2 x ∆V
may vary over the range of slew
STEP
voltage thresholds are exceeded.
dv
dt
t3
, which are the times when V
IN
OUT
t4
values should be used to vali-
ramp that will cause V
fraction of ∆V
, and C
OUT
C
reaches 2 or 3 times the
SC
OUT
] = (1-e
/ [(dV/dt) x τ
/ τ
to a V
STEP
C
and 4 x ∆V
IN
(-t / τL,eqv)
OUT
IN
in a graphical
ramp duration
Ramp
(max) is:
C
V
VOUT.F
])
IN
)
SC
OUT
/ τ
OUT
CB
C
IN
to
.
,