MAX5936ACESA+T Maxim Integrated Products, MAX5936ACESA+T Datasheet - Page 14

• Manufacturer Part Number: MAX5936ACESA+T
• Description: IC HOT-SWAP CTRLR -48V 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Hot-Swap Controllerr

Specifications of MAX5936ACESA+T

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: -10 V ~ -80 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

-48V Hot-Swap Controllers with V
Step Immunity and No R
This occurs with the least possible disturbance to V
although during the brief period that the MOSFET is off,
the voltage across the load droops slightly depending
on the load current and load storage capacitance.
PGOOD remains asserted throughout the V
event.
The objective in selecting the resistor and capacitor for
the step monitor function is to ensure that the V
of all anticipated slopes and magnitudes will be proper-
ly detected and blocked, which otherwise would result
in a circuit-breaker or short-circuit fault. The following is
a brief analysis for finding the resistor and capacitor.
For a more complete analysis, see Appendix B.
Figure 13 is a functional diagram exhibiting the
elements of the MAX5936/MAX5937 involved in the
step immunity function. This block diagram shows the
parallel relationship between V
Each has an I*R component establishing the DC level
prior to a step. While it is referred to as a V
the dynamic response to a finite voltage ramp that is
of interest.
Figure 13. MAX5936/MAX5937 Step Immunity Functional Diagram
14
V
IN
______________________________________________________________________________________
STEP
C
R
STEP_MON
V
STEP_MON
STEP_MON
STEP_MON
GND
I
V
STEP
EE
OUT
GATE
NOTE: V
R
and V
DS,ON
SC
, V
STEP
I
STEP_OS
V
V
IN
CB
SC
CB
STEP_MON
, V
TH
step, it is
MAX5936
MAX5937
STEPTH
IN
IN
V
OUT
steps
, V
OUT
step
STEP_MON
STEP_DET
,
.
SC TRIP
, AND VOUT ARE REFERENCED TO V
SENSE
t
CB_DLY
Given a positive V
approximate response of V
where τ
lent time constant of the load that must be found empir-
ically (see Appendix B).
Similarly, the response of STEP_MON to a V
V
where τ
For proper step detection, V
STEP
V
the application). V
with adequate margin, ∆V
the tolerance of both I
R
∆V
STEP_MON
OUT
STEP_MON
STEP_MON
CB TRIP
TH
reaching V
C
STEP
V
prior to V
= C
OUT
(t) = (dV/dt) x τ
= R
is typically set to 100kΩ which gives a
for a worst-case high of 0.36V.
LOAD
(t) = (dV/dt) x τ
x R
CB
STEP_MON
MANAGEMENT
EE
IN
STEP_MON
CYCLE
OUT
GATE
+ R
LOW
.
STEP
FAULT
x R
(overall V
ramp with a ramp rate of dV/dt, the
IN
DS(ON)
STEP_OS
DS(ON)
reaching V
STEP
STEP_MON
OUT
x C
C
must be set below STEP
IN
C
LOAD
x I
and τ
STEP_MON
STEP_MON
x (1-e
ramp rates anticipated in
to V
(±8%) and R
x (1-e
LOAD
SC
ESR
IN
L
C
ESL
(-t / τ
, to accommodate
,eqv is the equiva-
(-t / τSTEP)
or within 1.4ms of
is:
L
.
,eqv)
must exceed
IN
STEP_MON
)
ramp is:
) + 10µA
LOAD
TH
.